IGBT Forum Discussions

1 &3. This development board has been discontinued due to design issues and is no longer available for sale, and we do not recommend any further reference to its related design, please understand.

2. Q4 is a PMOS, which serves as an anti-reverse connection protection circuit. Its gate is connected to a resistor to ground, and if a forward voltage is connected to the input, current flows through the body diode of the PMOS to the load side. If the forward voltage exceeds the voltage threshold of the PMOS, the channel conducts. This reduces the drain-source voltage ( _VDS ) of the PMOS, which reduces power consumption. A voltage regulator, BZV55-C13, is typically connected between the gate and source to prevent an overvoltage condition at the gate-source voltage ( _VGS ) and also to protect the PMOS from breakdown during input power fluctuations.

This board was released in '12, and now that the technology iteration of power supply design solutions is so rapid, it makes little sense to continue to reference a faulty board.

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Hello! We performed ltspice double pulse test simulations on Infineon's three IGBT chips (models IKW75N65EL5_L1, IKZA75N65RH5_L1, and IKZA75N65RH5_L1, respectively). We found that during the IGBT switching process, the waveform in Figure 2 shows that the gate voltage suddenly drops after the Miller platform. The gate voltage waveform of some chips even reached negative pressure during this drop. At the same time, the experimental and simulation waveforms can also correspond to the simulation waveforms. I don't know if this kind of waveform is normal, I'd like you to explain it.

ltspice simulation waveform

ltspice simulation

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Hello, what are the pins on top of the IGBT module in figure 1 below? Is there any correspondence between these terminals and the endpoints in figure 2?

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What is an alternative chip or solution to use IR25750LTRPBF (discontinued) to detect conduction voltage drop

The bus voltage is 400V, and the withstand voltage is about 600

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