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IGBT Forum Discussions

User17668
Level 2
5 replies posted 10 questions asked 5 questions asked
Level 2
Hi Infineon Team,
Can you please tell more about what needs to be considered if I do parallelization of IGBTs?

Thanks a lot.
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IGBT_JC
Moderator
Moderator 5 solutions authored 5 replies posted 5 sign-ins
Moderator
First, obviously it is recommend paralleling IGBTs of the same part number, i.e. same chip technology and package.

Then, the main target when designing with paralleled IGBTs is to ensure equal current sharing between them during operation. Otherwise, the current imbalance could damage the IGBT with higher current due to excessive power dissipation. The difference in static and dynamic performance of the paralleled IGBTs due to their electrical parameters distribution, together with a poor pcb layout and cooling system design, are the main issues to achieve an equal current sharing.

With regard to the static performance of IGBTs, the difference of VCEsat due to the typical parameter distribution, results in larger amount of current conduction for the lower VCEsat device. However, if the IGBT’s VCEsat increase as a function of junction temperature (positive temperature coefficient VCEsat), the current sharing is dynamically self-achieved. Thus, if high current flows through one paralleled IGBT, this causes an increase of junction temperature and hence, VCEsat increases and the current is shifted to other paralleled IGBT with lower VCEsat. Therefore, it is recommended IGBTs with positive temperature coefficient VCEsat for easy paralleling.

For the dynamic performance of the IGBTs, the current imbalance during switching events is due mainly to the distribution of switching times ton and toff, gate threshold voltage VGE(th) and its negative temperature coefficient, gate charge Qg, Miller capacitance Cres, and transfer characteristic. Then, to minimize this issue, it is recommended to use split gate resistor for the gate driver network and a very symmetrical pcb layout for the gate driver loop and the emitter power loop, and very small gate common emitter inductance. The split gate resistor connection, as shown in the figure, improves the dynamic current sharing compared to one common gate resistor reducing the parameters distribution and common emitter inductance effects.

In summary, for paralleling IGBTs it is recommended positive temperature coefficient VCEsat, split gate resistor using low tolerance resistors, symmetrical PCB layout for the gate driver loop and the emitter power loop, very small gate common emitter inductance, and cooling system with similar junction-heatsink thermal resistance.

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IGBT_JC
Moderator
Moderator 5 solutions authored 5 replies posted 5 sign-ins
Moderator
First, obviously it is recommend paralleling IGBTs of the same part number, i.e. same chip technology and package.

Then, the main target when designing with paralleled IGBTs is to ensure equal current sharing between them during operation. Otherwise, the current imbalance could damage the IGBT with higher current due to excessive power dissipation. The difference in static and dynamic performance of the paralleled IGBTs due to their electrical parameters distribution, together with a poor pcb layout and cooling system design, are the main issues to achieve an equal current sharing.

With regard to the static performance of IGBTs, the difference of VCEsat due to the typical parameter distribution, results in larger amount of current conduction for the lower VCEsat device. However, if the IGBT’s VCEsat increase as a function of junction temperature (positive temperature coefficient VCEsat), the current sharing is dynamically self-achieved. Thus, if high current flows through one paralleled IGBT, this causes an increase of junction temperature and hence, VCEsat increases and the current is shifted to other paralleled IGBT with lower VCEsat. Therefore, it is recommended IGBTs with positive temperature coefficient VCEsat for easy paralleling.

For the dynamic performance of the IGBTs, the current imbalance during switching events is due mainly to the distribution of switching times ton and toff, gate threshold voltage VGE(th) and its negative temperature coefficient, gate charge Qg, Miller capacitance Cres, and transfer characteristic. Then, to minimize this issue, it is recommended to use split gate resistor for the gate driver network and a very symmetrical pcb layout for the gate driver loop and the emitter power loop, and very small gate common emitter inductance. The split gate resistor connection, as shown in the figure, improves the dynamic current sharing compared to one common gate resistor reducing the parameters distribution and common emitter inductance effects.

In summary, for paralleling IGBTs it is recommended positive temperature coefficient VCEsat, split gate resistor using low tolerance resistors, symmetrical PCB layout for the gate driver loop and the emitter power loop, very small gate common emitter inductance, and cooling system with similar junction-heatsink thermal resistance.
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