Gate Driver TVS Diodes Use case ?

[owais19m]

Hello, 

 First Time Posting on Infinion , I bought  50 units of FF800R17KP4_B2 series IGBT's , before already doing that I designed my Desaturation Circuit Using the Avago ACPL series . Now Im reconsidering some changes .I found out this article of / MA300E17 https://www.infineon.com/dgdl/Infineon-Module_Adapter_Board_for_PrimePACK-ApplicationNotes-v01_02-EN....

First I wanted to know what these TVS diodes are used for circled Red , I cant make any sense of them, I think they are used for some kind of transient voltage suppression  ?. Now this Adapter boards were designed for FF1000R17IE4 series but  I believe the circuit would work for FF800R17KP4_B2 series aswell ? Also according to this what is the max Desat Voltage Limit Set for this Circuit where Driver Shutdown occurs? 

Thanks You ,

[AZIZ_HASSAN]

Hi,

Thank you for posting at Infineon community. Please refer my answers to your queries.

1) The TVS diodes in red circle are used for voltage clamping. It is a technique which keeps the transient overvoltage during turn off under limit. This overvoltage mainly occurs due to leakage inductance in the circuit.

2) Yes the circuit can be used for FF800R17KP4_B2 IGBT but need not to be 100% same. There could be some changes as per the requirement and suitability. Like in FF1000R17IE4, NTC is in built but not in FF800R17KP4_B2 so no need of NTC circuit. Similarly, FF1000R17IE4 is half bridge and hence high and low side driver is required but the later IGBT can be used in half bridge configuration or even in parallel etc.. So, based upon application, the circuit may change.

3) For the Vce sat for shutdown, I will confirm soon.

BR,

AZIZ HASSAN

[owais19m]

Thankyou AZIZ HASSAN for the reply , Yes they are for transient voltage suppression , for my use case , my DC link voltage would be Max 538v dc so the max Vce voltage would be 1200v but I deliberately bought the 1700v rated. This means that I would be using all 4 SMCJ188 Avalanche Diodes according to the MA300E17/12 Reference , but I don't understand what should I be looking there , the clamping voltage or breakdown voltage , for the latter ,when transient voltage occur the Gate will charge again when there's 328 v clamp X 4 = 1300v ?

Secondly Due to these Diodes there would be another extra 400ns in which the IGBT is in active state  , so what should my deadtime be ? I'm using a Deadtime of 1uS . 

3rd for the FF800R17KP4 series what should my Gate Resistance be in total ? I calculated about 5.6Ω for R1,R2,R3,R4  labeled in red, and R5,R6 would be 1.5Ω labeled in blue , can you confirm its correct ?  

4rth yes please Kindly confirm what the Vce saturation voltage would be for this application .

Again to lift any kind of confusion , yes I've bought the 1700v IGBT version , but my application is only for 1200v I just wanted to have a beefed up version , These will be used in 150kva welding inverters . I know I believe I'm asking very technical questions , but in applications where I'm using these ,I cannot risk destroying my 1320$ x2 IGBT's so I need to make sure what I'm doing is right. Otherwise I believe apart from the gate resistors and TVS diodes the adapter is universal ! 

[AZIZ_HASSAN]

Hi,

Thank you for the response and here are my points pertaining to your details.

1) First, may I know which device you are using  and what is your leakage inductance of your power module /stack (which causes overshoot in voltage). Because both the IGBT are different and if you are using FF800 one, may I know in which configuration (parallel or half bridge etc.) you are using because if the leakage inductance is high, it will effect the performance.

2) Generally for clamping, breakdown voltage is considered. And here you can consider clamping the voltage to  70 to 80% of the device breakdown voltage and design accordingly. Yes when transient occur,  gate will charge but I did not get what is 328v clamp x 4= 1300? Please explain.

3) May I know how much you need dead time in your system because it is not just dependent upon your hardware parameters but also on control parameters. Like, if you use too high dead time, then from hardware point of view, diode will be stressed and also the current and voltage waveform (especially fundamental component may be bad). Moreover, the time 400 nsec. can be optimized if you check your leakage inductance  and then no need of adjusting dead time. These diode has less effect on dead time. Even 1usec. is still fine if your waveform is ok and diode is not overstressed.

I hope you understood this point, If not then please let me know.

4) I will get back to you with Vce. sat value. However, may I know why you need this value.  If you need this reference value for your design, it can be decided by other experimental means also.

BR,

AZIZ HASSAN

[owais19m]

Thankyou Aziz,

1) Stray Inductance for the FF800R17KP4_B2 is 20 nH , for my own circuit for the gate drive , consider it the MA300E/12 version which will be directly mounted on IGBT, FF800R17KP4 comes in Parallel version not Half Bridge version ,My Topology is a 2 Level Inverter  so basically I would need to FF800's with two Gate Drivers.Now if your asking the exact value of stray inductance of the circuit , that could be difficult to analyze for me but I've designed the gate drive section according to the MA300E as ive said before , taking care of all the traces as close as possible , Low Gate Resistor values , Also can you confirm my Resistor values are correct ?

The actual Problem is the 150KVA Transformer thats directly connected to the Output of the IGBT's that produces the transient voltages due to leakage inductances , For that I've used Snubbers networks across the IGBTS's and the input Transformer .

2) By the 328v clamp x 4= 1300v I meant that the SMJ188A TVS diode's clamping voltage is 328v  so since 4 are connected thats 1300v ,But your since your saying breakdown voltage is considered then that is Max Breakdown voltage 230v x 4 = 920v , so basically when 920v are induced the gate will be charged and conduct for extra period of time which is 400ns according to MA300E , reducing the di/dt ? .

3) Max DeadTime is 1uS ,my only concern was the extra conduction time when gate signal is high due to the TVS Diodes . 

4) I need the Vce Saturation value because I want to know when the Desat Circuit Turns the Transistors off due to saturation voltages , Basically Im using the ACPL332 IC  which has an internal reference of 6.5v , not 9v like the infinion Desat Ic's 

[AZIZ_HASSAN]

Hi,

Based upon the information shared, please find my below comments.

1) Great to here that you have optimized the gate path leakage inductance. However,  I was talking about power circuit leakage inductance (which causes overshoot in Vce voltage during turn off). Since, you are using in parallel configuration, I strongly suggest to optimize your power circuit leakage inductance. In data sheet of FF800 , 50nH is mentioned which is a tested value. If you keep it below 50 or close to  it is good enough. Regarding gate resistor, again its mentioned in data sheet that Rgon= 0.8 ohm and Rgoff= 1.8 ohm. 

2)  I would like to clarify that I  was talking about maximum breakdown voltage of device i.e. IGBT not TVS diode. So, please design your clamping circuit (TVS diode selection) up to 70-80% of the device maximum breakdown voltage( which is 1700V). Rest your understanding and calculation is correct regarding this point. 

3) Yes you are right theoretically, but  I request you to check the circuit in practical and measure how much  extra conduction is coming because it may vary as per temperature and other conditions. Apart from this , since your dc voltage is 538V, I would like to suggest you to optimize your power circuit leakage inductance and design your clamping circuit voltage (more than dc voltage + voltage due to leakage inductance ) in such a way that in every cycle, the system doesn't go in clamping mode at nominal operating current value. If this happens, then you need not to think about extra conduction time and dead band.

I hope you understood.

4) I got your context for Vce sat value. The Desat voltage is nearly 8V for this application. You can even change this value by adjusting the diode or resistor value in DESAT circuit.

Please let me know if I could help you more.

BR,

AZIZ HASSAN

[owais19m]

1) Can you give any example of optimizing leakage inductance in the power circuit ? Maybe Im missing on something .

4) Regarding Vce sat for the MA300E/12 ,at what Vce Saturation voltage is this IGBT turning off ? can you kindly confirm because I'm confused. For FF800R17KP4_B2 at 800A the typical Vce Sat is 2.1V , what is MA300E12/17 Vce sat shutting down at ? I think I'm misunderstanding this part , should I be switching off at Ic 800A or Ic repetitive which is 1600A . You would ask that depends on the Requirement ? , for that  My max continuous Amps are around 400A, but the sake of simplicity lets just talk about 800A-> Vce sat 2.1v at 150 degrees. 

Edit : At what Saturation voltage is the circuit turning off if Desat voltage is nearly 8v?  

[owais19m]

1) Can you give any example of optimizing leakage inductance in the power circuit ? Maybe Im missing on something .

4) Regarding Vce sat for the MA300E/12 ,at what Vce Saturation voltage is this IGBT turning off ? can you kindly confirm because I'm confused. For FF800R17KP4_B2 at 800A the typical Vce Sat is 2.1V , what is MA300E12/17 Vce sat shutting down at ? I think I'm misunderstanding this part , should I be switching off at Ic 800A or Ic repetitive which is 1600A . You would ask that depends on the Requirement ? , for that  My max continuous Amps are around 400A, but the sake of simplicity lets just talk about 800A-> Vce sat 2.1v at 150 degrees. 

Edit : At what Saturation voltage is the circuit turning off if Desat voltage is nearly 8v?  

[AZIZ_HASSAN · Accepted solution]

Hi,

1) Sorry I don't have any example for now. But I want to give a brief about it. Optimizing means adjusting the leakage inductance in such a way that the overshoot during turn off in voltage is less and also if the devices are connected in parallel, then the current sharing has to be equal or difference in collector/emitter current should be in limit. Both the points can be assured on experimental basis only. 

2) Generally, De sat detection threshold voltage is chosen at knee voltage which is near about 6-10 V for IGBT.  The circuit used for de sat detection has the equation as 

where Vz =0 (no zener in schematics), n=1(since only one diode in schematic) and Rlim =1 ohm (in schematic). Vce desat is called as effective threshold. As per the data available, calculation says that the DESAT actual is near about 8V.

This the circuit used for detection and the equation is derived from kVL.

I hope you understood now.

BR,

AZIZ HASSAN

[AZIZ_HASSAN]

Hi,

One more point i want to add is, the Ic vs Vce graph shared by you is correct for knowing the knee voltage. Knee voltage means the voltage at which the current saturates. But, in graph at Vge=15V, the current doesn't saturate at 800 A or at 1600A. so, it's not the detection de sat voltage. Please refer the diagram below for your understanding.

BR,

AZIZ HASSAN

[owais19m]

Thankyou for answering my questions , I understand now !