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YuTa_4942221
Level 4
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Level 4

Hi,  Please tell me about F3L400R07W3S5_B59.

If you check the internal circuit diagram, the IGBTs on the High side and Low side of the 3-level circuit are configured in parallel. What is the reason for this?

 

Modul number:F3L400R07W3S5_B59

https://www.infineon.com/dgdl/Infineon-F3L400R07W3S5_B59-DataSheet-v01_00-JA.pdf?fileId=8ac78c8c7c72...

 

Regards, 

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BandaruAkhil
Moderator
Moderator 50 sign-ins 25 replies posted 10 solutions authored
Moderator

 Hi @YuTa_4942221 

In light load conditions if two switches are operated in parallel the switching loss will be slightly

more compared to the single switch loss. But ultimately the losses will depend on the ON & OFF

strategy (PWM technique).

The main reason to provide a configuration like this is chips are fast and they do not have internal

gate resistors. We need separate Gate Emitter pins for better controllability and paralleling.

Please feel free to contact me if any other details are required.

 

Best Regards,

Akhil Kumar.

View solution in original post

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BandaruAkhil
Moderator
Moderator 50 sign-ins 25 replies posted 10 solutions authored
Moderator

Hi @YuTa_4942221 

Thanks for posting on the Infineon community page.

To meet the required nominal current of 200A and especially with fast switching nature, it is

required to have two S5 chips in parallel.

In light load conditions, this module can be operated with a single switch to reduce the losses. 

Please let us know if any other details are required.

Thanks & Regards,

Akhil Kumar.

  

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YuTa_4942221
Level 4
First like given First like received 25 sign-ins
Level 4

Akhil Kumar-san

Is it okay to understand that the reason why the high side and low side gate terminals that are in parallel are not one but are configured separately is that they can be driven by one element under light load?
Also, I'm sorry for the lack of study, but could you please tell me the reason why the loss is reduced by one element in the case of light load?

Regards, 

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BandaruAkhil
Moderator
Moderator 50 sign-ins 25 replies posted 10 solutions authored
Moderator

 Hi @YuTa_4942221 

In light load conditions if two switches are operated in parallel the switching loss will be slightly

more compared to the single switch loss. But ultimately the losses will depend on the ON & OFF

strategy (PWM technique).

The main reason to provide a configuration like this is chips are fast and they do not have internal

gate resistors. We need separate Gate Emitter pins for better controllability and paralleling.

Please feel free to contact me if any other details are required.

 

Best Regards,

Akhil Kumar.

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