Hyper RAM Forum Discussions
I asked the same question under HyperFlash board; however, this applies to the HyperRAM too since they follow the HyperBus timing specification all together.
Here is the link to the question: (Please review it, I'm not pasting it here to not to duplicate)
For the CLK, DQ and RWDS timings, it seems like the datasheet values are valid only up to ~65 MHz, although it is specified up to 133 MHz. Delay values and the valid areas of given signals doesn't add up and there seems to be a mismatch.
Has anyone ever tried to design the interface themselves or debugged the interface above ~65 MHz (CLK)? I'd like to see the DQs and RWDS signals (measured) above these clock frequencies.
Thank you.Show Less
The demo showcases the HyperRAM in Industrial or consumer HMI application as an expansion Memory in Display Applications. This demo demonstrates the HyperRAM throughput and density-fit in HMI applications in a low pin count compared to traditional SDR or parallel Async interface PSRAM solutions.
This is home automation where RGB LED (light, intensity), FAN speed, Temperature are remotely controlled/monitored by the HMI unit.
HMI unit uses a TFT display of size 480x272, 16-bit RGB pixel. This corresponds to 2Mbit per frame. Since display is SRAM intensive, internal SRAM is not sufficient in mid range controllers. The external HyperRAM memory is used for display buffer due to low pin count and high throughput.
Demo uses double buffering scheme where one frame is used to update anew display content while the other frame is directly driving the display content. Both frames are stored in HyperRAM. With high throughput of the HyperRAM demo, theoretically it can achieve up to 150fps.
For more details on HyperRAM Memory, click here.
I'm having trouble to test the Hyperbus Memory Controller IP which downloaded from cypress. I have read the ReadMeFirst pdf file and conducted the neccesary instructions. Yet there occurs some problems about .pl files I believe. The created log file only includes rpc2_ctrl_....... => UNDO. I am not sure whether simulation is successful or not. I want to observe a waveform of test. So if you have an example project (vivado) about test or simulation for Hyperbus Controller IP, could you share it with me?
I am trying to use hyperRAM in TE0725 board ...so I want to configure hyperRAM with microblaze core in xilinx vivado 2015.4 (webpack version)......... using your hyperRAM verilog file I have created IP (.xci) form......but after that I am not getting how to configure full IP ..... till now I am working on DDR3 RAM in Arty board ,............so please can you help me out how to configure it , send and receiver data through it......alsoI want one more thing to mention that when I have created IP it shows 198% of IO's (input/output)....can you explain this also....
maiL ID ---- email@example.comShow Less