Hyper RAM Forum Discussions
Hi,
I have designed a custom PCB with STM32H735 MCU and due to EoL and current unavailability of older HyperRAM S70KL1281 (that was originally used on ST-Micro's Discovery Kit) I decided to choose new HyperRAM S70KL1282. It's wired the same way as on discovery kit (including RWDS signal) and I was carefull about OSPI signal traces length matching.
I set up the MCU OSPI/HyperBus peripheral according to STM example and I use existing HyperRAM driver:
https://github.com/STMicroelectronics/stm32-s70kl1281
I fixed the initial latency from 6 to 7.
I can successfully read the device ID words and config reg 0,1.
The problem is that when I write some data at address 0 and read it back I found the data pattern writen with 8 bytes offset from the address 0 even I use always address 0 as argument to the R/W functions. I also tried enable memory mapped mode and access the RAM via pointer but I still got this strange offset. I also tried to lower the OSPI frequency by divider down to 33MHz but still any change. Contrary the users of old memory chip S70KL1281 doesn't report such problems. They shared the OSPI peripheral configuration that I tried to use so setting on MCU side (master) should be the same but I still have the 8B offset. I cannot get S70KL1281 to try. Any idea what's wrong? Do I need to set something in CR0/1 differently than POR values? Here are some of my code and debug terminal output to describe the issue:
{
uint8_t buff[64]={0};
int i;
buff[0]=0xab; buff[1]=0xcd; buff[2]=0xef; buff[3]=0xaa;
if (S70KL1281_Write(&XRAM, buff, 0, 16)!=S70KL1281_OK)
printf("Failed to write to HyperRAM\n");
for (i=0; i<32; i++)
printf("%02X ", buff[i]);
printf("\n");
if (S70KL1281_Read(&XRAM, buff, 0, 32)!=S70KL1281_OK)
printf("Failed to read from HyperRAM\n");
for (i=0; i<32; i++)
printf("%02X ", buff[i]);
printf("\n");
if (S70KL1281_Read(&XRAM, buff, 0, 32)!=S70KL1281_OK)
printf("Failed to read from HyperRAM\n");
for (i=0; i<32; i++)
printf("%02X ", buff[i]);
printf("\n");
}
The memory address is 0 but I get this:
Ext. OctoSPI HyperRAM ID: 0C81 0001
Manufacturer: Infineon, HyperRAM 2.0, rowbits: 13, colbits: 9
AB CD EF AA 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
57 47 57 5D D5 D7 8C 15 AB CD EF AA 00 00 00 00 00 00 00 00 00 00 00 00 D5 D5 57 5F D5 D5 5F 75
57 47 57 5D D5 D7 8C 15 AB CD EF AA 00 00 00 00 00 00 00 00 00 00 00 00 D5 D5 57 5F D5 D5 5F 75
There's some garbage in first 8 Bytes (57 47 57 5D D5 D7 CC 15 - uninitialized memory?) followed by correct pattern AB CD EF AA and trailing zeros from buffer
And the memory mapped mode:
{
__IO uint32_t *mem_addr = (__IO uint32_t *)(OCTOSPI2_BASE);
int i;
if (S70KL1281_EnableMemoryMappedMode(&XRAM)!=S70KL1281_OK)
printf("Failed to Enable Memory Mapped Mode\n");
else
printf("Memory Mapped Mode Enabled\n");
mem_addr[0]=0xABCDEFAA;
mem_addr[1]=0x12345678;
mem_addr[2]=0;
mem_addr[3]=0;
for (i=0; i<48; i++); // a shot delay, 46 read ok, 47 read garbage
printf("%08lX\n", mem_addr[0]);
printf("%08lX\n", mem_addr[0]);
printf("%08lX\n", mem_addr[0]); // 57 45 57 5D = "WEW]"
for (i=0; i<32/4; i++)
printf("%08lX ", mem_addr[i]);
printf("\n");
for (i=0; i<32; i++)
printf("%02X ", ((uint8_t *)mem_addr)[i]);
printf("\n");
}
Output is:
Ext. OctoSPI HyperRAM ID: 0C81 0001
Manufacturer: Infineon, HyperRAM 2.0, rowbits: 13, colbits: 9
Memory Mapped Mode Enabled
ABCDEFAA - this read changes according to for loop short delay, for shorter times it reads ABCDEFAA, for longer times it reads 5D574557
5D574557
5D574557
5D574557 158CD7D5 ABCDEFAA 12345678 00000000 00000000 5F57D5D5 755FF5D5
57 45 57 5D D5 D7 8C 15 AA EF CD AB 78 56 34 12 00 00 00 00 00 00 00 00 D5 D5 57 5F D5 F5 5F 75
Please let me know other users of this memory chip if it works for you properly or not and on what MCU/platform.
Is there any sample code or user guide for S70KS1283GABHI023 to program?
Deep power down will cause memory data to be lost, If you want to keep the data, you need to supply standby current Max. If you want to keep the data, you need to supply standby current Max250μA, is that correct?
Show Lessinitially it was configured as 8MB , and ran the hyper ram test code. Test was passed i could access the whole 8MB.
Later i tried to increase the memory configuration as 16MB, could not access the memory after first 8MB.
Am i missing any configurations ??
Show LessHi,
I would like to confirm if S27KL0642 are exactly the same as S27KL0643 as the hardware. If yes, is the only different thing to perform each test program for Octal x SPI interface and HYPERBUS interface ?
Best regards,
Show LessHi Team,
One of the project, I have interfaces hyperRAM S27KS0641DPBHI020 to croslink-NX FPGA. I have hyperram controller IP provided by infineon. I have written AXI master to communicate with hyperram controller IP which acts as a AXI slave.
Using AXI master, I am writing 0x00000000, 0x00000013 and 0x00000001 to registers of IP MBAR0, MCR0 and MTR0 respectively and readback successfully.
where 0x00000000 is base address to write/read data in hyperRAM.
value 0x00000013 to MCR0 to mention device type as hyperRAM i.e. MCR0[4] = 1.
value 0x00000001 to mention initial delay of 6 CLK same as bit 7 to bit 4 of configuration register (CR0) mapped to bit 3 to bit 0 of MTR0.
Even I tried by writing 0x00000033 first to MCR0 address and written value as above to MBAR0 and MTR0 then updated MCR0 to 0x00000013 so that command address CA[46] got mapped with MCR0[5] first 1 for register space then memory space.
I kept reset width of 1 sec for reset IP and delay of 1 msec between IP registers configuration and data write, also 1 msec between data write and read.
Unfortunately, despite IP registers MCR0, MTR0 and MBAR0 gets configured to value mantioned above I am unable to read data which written to memory, I am not sure data is being written to hyperram or not.
I am requesting for help in this regard, I stuck in between, I am trying to resolve using datasheet of hyperram but could not solve it. Please guide and suggest how can I resolve it for read and write to memory. I am getting all the signal properly on ILA expect read data.
Thanks,
Krishna
Show LessI have interfaced 64MB hyperRAM (S27KS0641DPBHI020) with FPGA on board. I am using infineon controller, I have written master to handle hyperram slave controller. I am getting expected result in simulation but not unable to read/ write data on actual hardware.
I have successfully write and read configuration registers, but data is not getting written and read back. I have reset for 10 sec which is much more than 300 microsec and provided delay of 1 sec between registers configuration and data write and lso between data write and data read.
Please suggest proper solution.
Show LessHi
Does HyperRAM products family have the function of embedded ECC ?
or do you have a plan to build the ECC function in the near future ?
I can not see that in description of datasheet.
Best regards,
Show Less
1. The timing diagram show a referesh collision during a write cycle. RWDS changes mid command. Is this expected behavior or a simulation bug? Where is the ideal point to sample RWDS for extended latency? It is not clear in the datasheet.
2. In past posts, my questions resulted in updates to the verilog model with respect to refresh collisions. I recently downloaded the most recent model, labelled 4.0, and find that it is not the most recent model I was personally given by infineon on this forum.
Show Less