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Hello,
We are using the S70KL1282 HyperRAM chip with the i.mx rt 1064 and for now we've only been using the IP Bus. We've managed to read all registers on the part shown below:
FlexRAM Config Reg0 - Die 0: 0x8f2f
FlexRAM Config Reg0 - Die 1: 0x8f2f
FlexRAM Config Reg1 - Die 0: 0xffc1
FlexRAM Config Reg1 - Die 1: 0xffc1
FlexRAM Die Manuf - Die 0: 0x3030
FlexRAM Die Manuf - Die 1: 0x3030
FlexRAM ID Reg0 - Die 0: 0x0c81
FlexRAM ID Reg0 - Die 1: 0x4c81
FlexRAM ID Reg1 - Die 0: 0x0001
FlexRAM ID Reg1 - Die 1: 0x0001
I've hooked up a scope and writing the data all seems correct, however on the read I am always getting 4 bytes of "garbage" data, in this case 0x0051dd5d. I've mostly been trying to read/write from memory address 0, but it seems I always get the "garbage" bytes with any memory address. Any help or suggestions on where to go would be appreciated.
Show LessCan i know where to find IBIS ver5.0 model (with power aware feature) for S27KS0643? Thank you!
In Hyper-V what happens when I "delete saved state" of one Remote PC; Would I lose the data in that Remote PC? Because I have tried to increase the RAM but it didn't work.
Show LessAre there IBIS models available for S27KS0642GABHV020? I've been searching through the website and unable to find any.
Hi,
Could you please provide the IBIS model for S70KS1281DPBHV020?
Best Regards,
Kumada
Hello,
I'm using this part in my design S70KL1283GABHB020.
Could you please share design guidelines, reference schematic, and simulation model for this part?
Show LessWe are looking for a way to integrate external RAM (possibly as large as 16MB) in our Project. Right now, we can only use Quad-SPI to connect the RAM-IC to our µC.
After looking at the Datasheets for the S27-Series, I haven't found a possibility to set the ICs up for a Quad-I/O-Mode.
Can you confirm that, or is there a way that i have overlooked?
The Exelon F-RAMs seem to be compatible with QSPI, though the Memory Density is not as large as we might need it.
Is there another product, that we could use?
Thank you and regards,
Fabian
Show LessHello everyone,
I asked the same question under HyperFlash board; however, this applies to the HyperRAM too since they follow the HyperBus timing specification all together.
Here is the link to the question: (Please review it, I'm not pasting it here to not to duplicate)
For the CLK, DQ and RWDS timings, it seems like the datasheet values are valid only up to ~65 MHz, although it is specified up to 133 MHz. Delay values and the valid areas of given signals doesn't add up and there seems to be a mismatch.
Has anyone ever tried to design the interface themselves or debugged the interface above ~65 MHz (CLK)? I'd like to see the DQs and RWDS signals (measured) above these clock frequencies.
Hopefully, @BushraH_91 , @TakahiroK_16 or other employees can answer. In the meantime, please feel free to comment if you're experienced on the topic.
Thank you.
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