Hyper RAM Forum Discussions

Hello,

We are using the S70KL1282 HyperRAM chip with the i.mx rt 1064 and for now we've only been using the IP Bus. We've managed to read all registers on the part shown below: 

FlexRAM Config Reg0 - Die 0: 0x8f2f
FlexRAM Config Reg0 - Die 1: 0x8f2f
FlexRAM Config Reg1 - Die 0: 0xffc1
FlexRAM Config Reg1 - Die 1: 0xffc1
FlexRAM Die Manuf - Die 0: 0x3030
FlexRAM Die Manuf - Die 1: 0x3030
FlexRAM ID Reg0 - Die 0: 0x0c81
FlexRAM ID Reg0 - Die 1: 0x4c81
FlexRAM ID Reg1 - Die 0: 0x0001
FlexRAM ID Reg1 - Die 1: 0x0001

I've hooked up a scope and writing the data all seems correct, however on the read I am always getting 4 bytes of "garbage" data, in this case 0x0051dd5d. I've mostly been trying to read/write from memory address 0, but it seems I always get the "garbage" bytes with any memory address. Any help or suggestions on where to go would be appreciated. 

Hello, 

I'm using this part in my design S70KL1283GABHB020. 

Could you please share design guidelines, reference schematic, and simulation model for this part? 

If I have the previledge to buy a cheaper 3000mhz ram over a more expensive 2666mhz(the fastest speed of cpu support) both same size 16gb, will it work if i downclock it to 2666mhz through bios? Or will i have issues?

I'm using the product S70KL128, but the document were not found, Could you help me to find it.

Thanks!

We are looking for a way to integrate external RAM (possibly as large as 16MB) in our Project. Right now, we can only use Quad-SPI to connect the RAM-IC to our µC.

After looking at the Datasheets for the S27-Series, I haven't found a possibility to set the ICs up for a Quad-I/O-Mode.
Can you confirm that, or is there a way that i have overlooked?

The Exelon F-RAMs seem to be compatible with QSPI, though the Memory Density is not as large as we might need it.
Is there another product, that we could use?

Thank you and regards,

Fabian

Hi,

we are using two S27KS0642 as ping-pong buffers for a USB3 application (commercial temperature)

We will be driving them to their performance limits (so the full 3.2Gbit/s).
In order to achieve the maximum performance and reduce complexity we would like to violate the Tcsm.
(I understand, that this should be possible as long as we ensure the refresh of all cells)

Our major scenario will be the following: 
1. Write the complete memory
2. Read the complete memory within 40ms maximum
3. (Possibly) read the complete memory again within 40ms maximum

As far as I understand the behavior of the memory it should be fine to violate Tcsm as long as we ensure, that the complete memory is read/written within 64ms. 

Am I correct with that assumption or are there any problems to expect?

We have a second scenario (USB2.0/1.0 fallback) that will be:
1. Write the complete memory (ignoring Tcsm)
2. Read the complete memory in smaller junks honoring Tcsm

I would assume, that writing the complete memory will cause a complete refresh and that afterwards the self refresh operation will start running as before?

Best regards
Bernhard Wörndl-Aichriedler