Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

Hyper RAM Forum Discussions

Recent discussions

Sort by:
Braycarl
Hyper RAM
In Hyper-V what happens when I "delete saved state" of one Remote PC; Would I lose the data in that Remote PC? Because I have tried to increase the RA... Show More
Berkj
Hyper RAM
Hello everyone, I asked the same question under HyperFlash board; however, this applies to the HyperRAM too since they follow the HyperBus timing spec... Show More
GoKo_4683011
Hyper RAM
Hello, We are using the STM32L4R5 (Nucleo-144, L4R5ZI-P) to implement HyperRAM memory (S27KL0642) under hyperbus protocol. There is a problem between ... Show More
pf_arc
Hyper RAM
We are using a Cypress/Infineon HyperRAM, part number S70KS1281DPBHV020, driven by the Cypress/Infineon Hyperbus Controller on a Xilinx FPGA (xc7k160t... Show More
Stark38
Hyper RAM
Hi, I'm trying to implement Hyperbus protocol for Hyper RAM on a NUCLEOL4R5ZI-P without success. Is some exemple on STM32L4R are available?   Kind reg... Show More
ToIk_1341346
Hyper RAM
70KS1281DPBHI020(HyperRAM)について、相談させて下さい。 上記は型式として1.8V品となっていますが、AC性能を3V品相当とすれば、3V品として使用可能でしょうか。 (DDR3LをDDR3として使用するように。)   背景としては、試作基板で使用しており他の設計ミスのためB... Show More
GirijaC_46
Hyper RAM
The demo showcases the HyperRAM in Industrial or consumer HMI application as an expansion Memory in Display Applications. This demo demonstrates the H... Show More
prbh_4725631
Hyper RAM
Hello,  I am working on iMX8QXP based custom board with Yocto L5.4.24-2.1.0.On our board, we are trying to communicate S27KS0641 HyperRAM using the Fl... Show More
user_4746276
Hyper RAM
Hi,I'm having trouble to test the Hyperbus Memory Controller IP which downloaded from cypress. I have read the ReadMeFirst pdf file and conducted the ... Show More
brle_3072681
Hyper RAM
HI,I use the S27KS0641's model emulate the controller,but Modelsim hint "Error: C:/Users/Bruce/Desktop/Psram_Interface/s27ks0641.v(375): $skew( neged... Show More
Forum Information

Hyper RAM

HyperRAM™ memory Forum discusses self-refresh DRAM operating on the 12-pin HyperBus interface. With a read throughput up to 333 MB/s, the HyperRAM for SoCs with limited on-board RAM providing external scratch-pad memory for fast read and write operations.