In Hyper-V what happens when I "delete saved state" of one Remote PC; Would I lose the data in that Remote PC? Because I have tried to increase the RAM but it didn't work.Show Less
I asked the same question under HyperFlash board; however, this applies to the HyperRAM too since they follow the HyperBus timing specification all together.
Here is the link to the question: (Please review it, I'm not pasting it here to not to duplicate)
For the CLK, DQ and RWDS timings, it seems like the datasheet values are valid only up to ~65 MHz, although it is specified up to 133 MHz. Delay values and the valid areas of given signals doesn't add up and there seems to be a mismatch.
Has anyone ever tried to design the interface themselves or debugged the interface above ~65 MHz (CLK)? I'd like to see the DQs and RWDS signals (measured) above these clock frequencies.
Thank you.Show Less
We are using the STM32L4R5 (Nucleo-144, L4R5ZI-P) to implement HyperRAM memory (S27KL0642) under hyperbus protocol. There is a problem between OCTOSPI and serial communication. Sometimes, when the OCTOSPI is being activated the serial port doesn't work.
Any help will be appreciated.
We are using a Cypress/Infineon HyperRAM, part number S70KS1281DPBHV020, driven by the Cypress/Infineon Hyperbus Controller on a Xilinx FPGA (xc7k160t-2ffg676) at 100 MHz. On said FPGA is also a soft-microcontroller (MicroBlaze) that uses the HyperRAM as instruction memory.
We have issues with erratic behaviour of the MicroBlaze after some time passes, usually several days. When we read back the processor’s instruction memory we see that entire blocks have been corrupted. We see that the corrupt blocks are 1024 bytes in size and are located at offsets of 1024 bytes as well. According to the HyperRAM component’s datasheet, the RAM is organized in 16384 rows of 1024 bytes. It appears that the corrupt memory blocks all contain the same data after the fact.
We have ensured that no write access has taken place to the instruction memory, so it must have changed spontaneously. We have also verified that we do not violate the RAM's tCMS and are also providing additonal latency for refresh cycles with every single access. As far as we know, the FPGA drives the HyperRAM according to specifications.
We have reviewed our schematics and have noticed a few issues that however don't seem to be very critical:
- We have added pull up resistors on the pins A2 (RSTO#) and A5 (INT#), which are marked as “RFU” in the HyperRAM datasheet. In the FPGA, they are unused so there is a weak pull-down (10-40k if I’m not mistaken) by default. In the Documentation of the Infineon/Cypress/Spansion HyperBus Controller, I found the following passage regarding the INT and RSTO pins, which might be the reason we have added those:
- On the A4 pin (RESET#), we have a pull down resistor, but in the datasheet, Cypress/Infineon indicates that there is an internal weak pull up resistor in the HyperRAM. During normal operation, this signal is driven by the FPGA, however.
- The B5/C5 pins (PCS/PCS#) are RFU in the datasheet as well but are unconnected in the FPGA, which means there is a weak pulldown there as well.
- The C2 pin (CS1) is RFU in the datasheet but driven high by the FPGA.
- We have also noticed that our Power Delivery trace widths are 11.8 mils wide, which is below the recommended 20 mils in the Design Guide you’ve sent.
We are driving the CK/CK# as two phase-shifted clocks, not through a differential buffer as the schematics might suggest. The schematics also show an ISSI HyperRAM part, but we are experiencing the exact same issue with that one.
What could be the cause of this?Show Less
I'm trying to implement Hyperbus protocol for Hyper RAM on a NUCLEOL4R5ZI-P without success. Is some exemple on STM32L4R are available?
Kind regardsShow Less
The demo showcases the HyperRAM in Industrial or consumer HMI application as an expansion Memory in Display Applications. This demo demonstrates the HyperRAM throughput and density-fit in HMI applications in a low pin count compared to traditional SDR or parallel Async interface PSRAM solutions.
This is home automation where RGB LED (light, intensity), FAN speed, Temperature are remotely controlled/monitored by the HMI unit.
HMI unit uses a TFT display of size 480x272, 16-bit RGB pixel. This corresponds to 2Mbit per frame. Since display is SRAM intensive, internal SRAM is not sufficient in mid range controllers. The external HyperRAM memory is used for display buffer due to low pin count and high throughput.
Demo uses double buffering scheme where one frame is used to update anew display content while the other frame is directly driving the display content. Both frames are stored in HyperRAM. With high throughput of the HyperRAM demo, theoretically it can achieve up to 150fps.
For more details on HyperRAM Memory, click here.
I am working on iMX8QXP based custom board with Yocto L5.4.24-2.1.0.
On our board, we are trying to communicate S27KS0641 HyperRAM using the FlexSPI interface. I did not find any driver specific to this which I can use.
So I have created my own driver inspired by spi_nor.c. After adjusting the dummy bytes I am able to read the ID register, read-write the Configuration register. But I am not able to correctly(with 100% accuracy) read-write data to/from memory.
Is there anything I am doing wrong?
Is there any driver which uses hyperbus interface and communicates to the memory connected to the flexSPI interface?
I'm having trouble to test the Hyperbus Memory Controller IP which downloaded from cypress. I have read the ReadMeFirst pdf file and conducted the neccesary instructions. Yet there occurs some problems about .pl files I believe. The created log file only includes rpc2_ctrl_....... => UNDO. I am not sure whether simulation is successful or not. I want to observe a waveform of test. So if you have an example project (vivado) about test or simulation for Hyperbus Controller IP, could you share it with me?
I use the S27KS0641's model emulate the controller,but Modelsim hint "Error: C:/Users/Bruce/Desktop/Psram_Interface/s27ks0641.v(375): $skew( negedge CSNeg:41697163 ps, posedge CSNeg:42007173 ps, 1 ps );".The ck is 100MHz,and only Write 32 bytes,we have provided 12 cycles of latency. There is only 310ns from the negedge of CS to the posedge of CS.What the error tell us?Thank you.Show Less