Hyper RAM Forum Discussions

Hi Team,

    One of the project, I have interfaces hyperRAM S27KS0641DPBHI020 to croslink-NX FPGA. I have hyperram controller IP provided by infineon.  I have written AXI master to communicate with hyperram controller IP which acts as a AXI slave.  

Using AXI master, I am writing 0x00000000, 0x00000013 and 0x00000001 to registers of IP MBAR0, MCR0 and MTR0 respectively and readback successfully.

where 0x00000000 is base address to write/read data in hyperRAM.  

value 0x00000013 to MCR0 to mention device type as hyperRAM i.e. MCR0[4] = 1.

value 0x00000001 to mention initial delay of 6 CLK same as bit 7 to bit 4 of configuration register (CR0) mapped to bit 3 to bit 0 of MTR0.

Even I tried by writing 0x00000033 first to MCR0 address and written value as above to MBAR0 and MTR0 then updated MCR0 to 0x00000013 so that command address CA[46] got mapped with MCR0[5] first 1 for register space then memory space.

I kept reset width of 1 sec for reset IP and delay of 1 msec between IP registers configuration and data write, also 1 msec between data write and read. 

Unfortunately, despite IP registers MCR0, MTR0 and MBAR0 gets configured to value mantioned above I am unable to read data which written to memory, I am not sure data is being written to hyperram or not. 

I am requesting for help in this regard, I stuck in between, I am trying to resolve using datasheet of hyperram but could not solve it. Please guide and suggest how can I resolve it for read and write to memory. I am getting all the signal properly on ILA expect read data. 

Thanks,

Krishna

I have interfaced 64MB hyperRAM (S27KS0641DPBHI020) with FPGA on board.  I am using infineon controller, I have written master to handle hyperram slave controller. I am getting expected result in simulation but not unable to read/ write data on actual hardware. 

I have successfully write and read configuration registers, but data is not getting written and read back. I have reset for 10 sec which is much more than 300 microsec and provided delay of 1 sec between registers configuration and data write and lso between data write and data read.

Please suggest proper solution. 

1. The timing diagram show a referesh collision during a write cycle. RWDS changes mid command. Is this expected behavior or a simulation bug? Where is the ideal point to sample RWDS for extended latency? It is not clear in the datasheet.

2. In past posts, my questions resulted in updates to the verilog model with respect to refresh collisions. I recently downloaded the most recent model, labelled 4.0, and find that it is not the most recent model I was personally given by infineon on this forum.

Hi

we see memory test failures when running memtest in an eternal loop, it happens about once a day, and once it was running a week without failures. So I wonder if anyone has run a long memory test on some FPGA board? What board? What IP was used? How long was the longest test run?

So far I see several reports that there are failures on running memory tests, from different people, different FPGA boards, and different IP cores.

I am currently using OpenHBMC:

https://github.com/OVGN/OpenHBMC

With this board:

https://shop.trenz-electronic.de/de/CR00107-01-CRUVI-carrier-board-with-AMD-Spartan-7

I do not think there is a signal integrity issue: all HyperBUS wires are between 2 and 4 mm in length. 

Thanks!

When I set up HyperBUS, it writes an indeterminate value (this is usually the case in the first generation as well).
When I write after this, I cannot write correctly.
I can't write directly in the debugger.
If I do a 16-byte write, for example, it appears that I can write from the middle.
When 16 characters are written as shown below, it seems to be able to write properly from the 5th character.
W: "HE2CT-1200A-3Z", R: "T-1200A-3Z
R: "T-1200A-3Z "

For example.
16 characters "HE2CT-1200A-3Z " should be
0x4000'0000~ and write
0x4000'0000～ is read in
If the character that should be in 0x4000'0004~ is written as
T-1200A-3Z" can be read.
This is the phenomenon.

If we follow the attached PCN and migration guidance document from Infineon, we need to set the latency to 7 clocks, but
RZ/A2M's latency clock setting seems to be only 5 or 6 clocks.

　In the migration of HyperRAM GEN2.0 to the current RZ/A2M MPU (R7S921053VCBG), the clock cycle difference seems to have a particular impact.
The clock cycle difference seems to have a particular impact.
Is it possible to apply RZ/A2M vs HyperRAM Gen.2 itself?

Translated with DeepL

Hello,

On our board we have one HyperRAM (S27KS064 1 DP B HB 02) and one HyperFlash (S26KS512S DP B HM 02).
These memories are connected to a FPGA through a shared bus (Y topology). FPGA implements one CYPRESS HyperBus controller that is connect to HyperFlash through first Chip Select and connected to HyperRAM connected second Chip Select. HyperBus memories at clocked by FPGA with a 100MHz clock.
At power-up, a controller inside FPGA initialize (in sequence) the HyperBus controller, HyperFlash and HyperRAM with following values:
• HyperBus controller
MTR0: 0x00110001
MTR1: 0x0011000F
MCR1: 0x807C0013
• HyperRAM CR0: 0xFFF5

During integration tests, we have some problem with the HyperRAM component.

First, we are not able to read the written value in CR0. Indeed, when we read the CR0 of HyperRAM we read always 0xFFFF or 0x5555.
When we change the written value of CR0 we can observe an impact on our tests. So we think that register has been correctly written, but a doubt persists. When the CR0 is not written at power-up, we read the default value (0x8F1F) described in the component datasheet but not on the first read access.


The second problem has been observed for high temperature (superior at 85°C). We have performed thermal tests of the HyperRAM but we observe than some data inside HyperRAM are corrupted. The number of corrupted data increase at each HyperRAM contents verification.
For information, this is the test procedure that we use:
• Write pseudo-random data in the HyperRAM (the all 8Mbytes of the memory is written)
• Read and verify the content of the memory
• Start again the Read and verify process

The test has been performed at a temperature of 95°C. Which correspond to a die temperature of 105°C for the FPGA and a temperature less than 105°C for the HyperRAM component. So we are in the operational range of the components.

To identify the problem source and to discard a refresh problem, we have perform a specific test which consist to
• At +25°C:
o Write pseudo-random pattern to memory
o Read&check pseudo-random pattern (ensure that there is no error)
• Without doing any HBRAM access:
o Increase temperature to +95°C
o Wait for 30 min
o Decrease temperature to +25°C
• Perform read&check test

During this test we have seen no error. So it’s not a refresh problem.

Moreover, to discard a timing problem, we have perform a test at 95°C without HyperRAM CR0 modification by adapting MTR1 and MCR1 values has follows for HyperBus Controller:
• MTR1: 0x00110001
• MCR1: 0x807D0013
CR0 reset value is 0x8F1F.
During this test, we have observed no error.

The both problem has been reproduced on the S27KS0641DPBHI020 (Industrial HyperRAM gen1) component at 85°C.

So for this moment, we cannot explain these two problems and through all performed tests we think that is not a timing problem.

Have you seen similar problems ?

Additionally, we have performed a test with HyperRAM gen2 component (7KS0642GAHI02).

With the same setup above and by replacing HyperRAM gen1 component by a HyperRAM gen2 component the problem identify on Configuration register 0 disappear. Indeed, with gen2 component we are able to write and read the CR0 register.

We have found an old datasheet of the component (001-97964 Rev. *E ) with an errata chapter.

The problem identify in this document is still valid ?

So, is there known issue on HyperRAM gen1 component ?

Is there an errata document ?

Thanks for your help
Jean

In Hyper-V what happens when I "delete saved state" of one Remote PC; Would I lose the data in that Remote PC? Because I have tried to increase the RAM but it didn't work.

Hello everyone,

I asked the same question under HyperFlash board; however, this applies to the HyperRAM too since they follow the HyperBus timing specification all together.

Here is the link to the question: (Please review it, I'm not pasting it here to not to duplicate)

Question - HyperFlash Board 

For the CLK, DQ and RWDS timings, it seems like the datasheet values are valid only up to ~65 MHz, although it is specified up to 133 MHz. Delay values and the valid areas of given signals doesn't add up and there seems to be a mismatch.

Has anyone ever tried to design the interface themselves or debugged the interface above ~65 MHz (CLK)?  I'd like to see the DQs and RWDS signals (measured) above these clock frequencies.

Hopefully, @BushraH_91 , @TakahiroK_16 or other employees can answer. In the meantime, please feel free to comment if you're experienced on the topic. 

Thank you.

Hello,

We are using the STM32L4R5 (Nucleo-144, L4R5ZI-P) to implement HyperRAM memory (S27KL0642) under hyperbus protocol. There is a problem between OCTOSPI and serial communication. Sometimes, when the OCTOSPI is being activated the serial port doesn't work.

Any help will be appreciated.