Hi

we see memory test failures when running memtest in an eternal loop, it happens about once a day, and once it was running a week without failures. So I wonder if anyone has run a long memory test on some FPGA board? What board? What IP was used? How long was the longest test run?

So far I see several reports that there are failures on running memory tests, from different people, different FPGA boards, and different IP cores.

I am currently using OpenHBMC:

https://github.com/OVGN/OpenHBMC

With this board:

https://shop.trenz-electronic.de/de/CR00107-01-CRUVI-carrier-board-with-AMD-Spartan-7

I do not think there is a signal integrity issue: all HyperBUS wires are between 2 and 4 mm in length. 

Thanks!

When I set up HyperBUS, it writes an indeterminate value (this is usually the case in the first generation as well).
When I write after this, I cannot write correctly.
I can't write directly in the debugger.
If I do a 16-byte write, for example, it appears that I can write from the middle.
When 16 characters are written as shown below, it seems to be able to write properly from the 5th character.
W: "HE2CT-1200A-3Z", R: "T-1200A-3Z
R: "T-1200A-3Z "

For example.
16 characters "HE2CT-1200A-3Z " should be
0x4000'0000~ and write
0x4000'0000～ is read in
If the character that should be in 0x4000'0004~ is written as
T-1200A-3Z" can be read.
This is the phenomenon.

If we follow the attached PCN and migration guidance document from Infineon, we need to set the latency to 7 clocks, but
RZ/A2M's latency clock setting seems to be only 5 or 6 clocks.

　In the migration of HyperRAM GEN2.0 to the current RZ/A2M MPU (R7S921053VCBG), the clock cycle difference seems to have a particular impact.
The clock cycle difference seems to have a particular impact.
Is it possible to apply RZ/A2M vs HyperRAM Gen.2 itself?

Translated with DeepL

Hello,

On our board we have one HyperRAM (S27KS064 1 DP B HB 02) and one HyperFlash (S26KS512S DP B HM 02).
These memories are connected to a FPGA through a shared bus (Y topology). FPGA implements one CYPRESS HyperBus controller that is connect to HyperFlash through first Chip Select and connected to HyperRAM connected second Chip Select. HyperBus memories at clocked by FPGA with a 100MHz clock.
At power-up, a controller inside FPGA initialize (in sequence) the HyperBus controller, HyperFlash and HyperRAM with following values:
• HyperBus controller
MTR0: 0x00110001
MTR1: 0x0011000F
MCR1: 0x807C0013
• HyperRAM CR0: 0xFFF5

During integration tests, we have some problem with the HyperRAM component.

First, we are not able to read the written value in CR0. Indeed, when we read the CR0 of HyperRAM we read always 0xFFFF or 0x5555.
When we change the written value of CR0 we can observe an impact on our tests. So we think that register has been correctly written, but a doubt persists. When the CR0 is not written at power-up, we read the default value (0x8F1F) described in the component datasheet but not on the first read access.


The second problem has been observed for high temperature (superior at 85°C). We have performed thermal tests of the HyperRAM but we observe than some data inside HyperRAM are corrupted. The number of corrupted data increase at each HyperRAM contents verification.
For information, this is the test procedure that we use:
• Write pseudo-random data in the HyperRAM (the all 8Mbytes of the memory is written)
• Read and verify the content of the memory
• Start again the Read and verify process

The test has been performed at a temperature of 95°C. Which correspond to a die temperature of 105°C for the FPGA and a temperature less than 105°C for the HyperRAM component. So we are in the operational range of the components.

To identify the problem source and to discard a refresh problem, we have perform a specific test which consist to
• At +25°C:
o Write pseudo-random pattern to memory
o Read&check pseudo-random pattern (ensure that there is no error)
• Without doing any HBRAM access:
o Increase temperature to +95°C
o Wait for 30 min
o Decrease temperature to +25°C
• Perform read&check test

During this test we have seen no error. So it’s not a refresh problem.

Moreover, to discard a timing problem, we have perform a test at 95°C without HyperRAM CR0 modification by adapting MTR1 and MCR1 values has follows for HyperBus Controller:
• MTR1: 0x00110001
• MCR1: 0x807D0013
CR0 reset value is 0x8F1F.
During this test, we have observed no error.

The both problem has been reproduced on the S27KS0641DPBHI020 (Industrial HyperRAM gen1) component at 85°C.

So for this moment, we cannot explain these two problems and through all performed tests we think that is not a timing problem.

Have you seen similar problems ?

Additionally, we have performed a test with HyperRAM gen2 component (7KS0642GAHI02).

With the same setup above and by replacing HyperRAM gen1 component by a HyperRAM gen2 component the problem identify on Configuration register 0 disappear. Indeed, with gen2 component we are able to write and read the CR0 register.

We have found an old datasheet of the component (001-97964 Rev. *E ) with an errata chapter.

The problem identify in this document is still valid ?

So, is there known issue on HyperRAM gen1 component ?

Is there an errata document ?

Thanks for your help
Jean

In Hyper-V what happens when I "delete saved state" of one Remote PC; Would I lose the data in that Remote PC? Because I have tried to increase the RAM but it didn't work.

Hello everyone,

I asked the same question under HyperFlash board; however, this applies to the HyperRAM too since they follow the HyperBus timing specification all together.

Here is the link to the question: (Please review it, I'm not pasting it here to not to duplicate)

Question - HyperFlash Board 

For the CLK, DQ and RWDS timings, it seems like the datasheet values are valid only up to ~65 MHz, although it is specified up to 133 MHz. Delay values and the valid areas of given signals doesn't add up and there seems to be a mismatch.

Has anyone ever tried to design the interface themselves or debugged the interface above ~65 MHz (CLK)?  I'd like to see the DQs and RWDS signals (measured) above these clock frequencies.

Hopefully, @BushraH_91 , @TakahiroK_16 or other employees can answer. In the meantime, please feel free to comment if you're experienced on the topic. 

Thank you.

Hello,

We are using the STM32L4R5 (Nucleo-144, L4R5ZI-P) to implement HyperRAM memory (S27KL0642) under hyperbus protocol. There is a problem between OCTOSPI and serial communication. Sometimes, when the OCTOSPI is being activated the serial port doesn't work.

Any help will be appreciated. 

Hi,

I'm trying to implement Hyperbus protocol for Hyper RAM on a NUCLEOL4R5ZI-P without success. Is some exemple on STM32L4R are available?

Kind regards

We are using a Cypress/Infineon HyperRAM, part number S70KS1281DPBHV020, driven by the Cypress/Infineon Hyperbus Controller on a Xilinx FPGA (xc7k160t-2ffg676) at 100 MHz. On said FPGA is also a soft-microcontroller (MicroBlaze) that uses the HyperRAM as instruction memory.

We have issues with erratic behaviour of the MicroBlaze after some time passes, usually several days. When we read back the processor’s instruction memory we see that entire blocks have been corrupted. We see that the corrupt blocks are 1024 bytes in size and are located at offsets of 1024 bytes as well. According to the HyperRAM component’s datasheet, the RAM is organized in 16384 rows of 1024 bytes. It appears that the corrupt memory blocks all contain the same data after the fact.

We have ensured that no write access has taken place to the instruction memory, so it must have changed spontaneously. We have also verified that we do not violate the RAM's tCMS and are also providing additonal latency for refresh cycles with every single access. As far as we know, the FPGA drives the HyperRAM according to specifications.

We have reviewed our schematics and have noticed a few issues that however don't seem to be very critical:Schematics

• We have added pull up resistors on the pins A2 (RSTO#) and A5 (INT#), which are marked as “RFU” in the HyperRAM datasheet. In the FPGA, they are unused so there is a weak pull-down (10-40k if I’m not mistaken) by default. In the Documentation of the Infineon/Cypress/Spansion HyperBus Controller, I found the following passage regarding the INT and RSTO pins, which might be the reason we have added those:
• On the A4 pin (RESET#), we have a pull down resistor, but in the datasheet, Cypress/Infineon indicates that there is an internal weak pull up resistor in the HyperRAM. During normal operation, this signal is driven by the FPGA, however.
• The B5/C5 pins (PCS/PCS#) are RFU in the datasheet as well but are unconnected in the FPGA, which means there is a weak pulldown there as well.
• The C2 pin (CS1) is RFU in the datasheet but driven high by the FPGA.
• We have also noticed that our Power Delivery trace widths are 11.8 mils wide, which is below the recommended 20 mils in the Design Guide you’ve sent.

We are driving the CK/CK# as two phase-shifted clocks, not through a differential buffer as the schematics might suggest. The schematics also show an ISSI HyperRAM part, but we are experiencing the exact same issue with that one.

What could be the cause of this?