Hyper RAM Forum Discussions
What is the MTBF / FITs spec for this part: S27KS0641DPBHV020
It is mentioned that:
4. A Row is a group of words relevant to the internal memory array structure and additional latency may be inserted by RWDS when crossing Row boundaries - this is
device dependent behavior, refer to each HyperBus device data sheet for additional information. Also, the number of Rows may be used in the calculation of a
distributed refresh interval for HyperRAM memory.
5. A Page is a 16-word (32-byte) length and aligned unit of device internal read or write access and additional latency may be inserted by RWDS when crossing Page
boundaries - this is device dependent behavior, refer to each HyperBus device data sheet for additional information.
What value of latency to use when crossing pages or rows?
Is this the initial latency before RD data out? or it is extra latency between rows or pages?
like RD data as: [RD data of row1] [Latency] [RD data of row2]
Show LessHi,
I try to integrate the verilog model for S27ks0641 with the synopsys SSI IP.
I got the following:
Warning! Timing violation
$skew( negedge CSNeg:414195 PS, posedge CSNeg:498597 PS, 1 : 1 PS );
File: s27ks0641.v, line = 369
Scope: ssi_tbe.mem_model
Time: 498597 PS
I modified the value in the verilog file of tskew_CSNeg_CSNeg from 1 (tCSM) to 100000 to avoid it.
we run in 166MHz and the time between fall(CSNeg) and rise(CSNeg) can not be 1 ps
not sure why this value was set to such a short time?
the skew command requires a time interval of 1 ps max for CS to be active - that is not enough to deliver a Hyperbus frame.
can you please clarify?
Best wishes,
Cluny
Show LessI'm interested in using an ARM microprocessor with a HyperBus interface attached to an FPGA; where the FPGA is a slave device with memory mapped registers that act as an extension of memory space to the uProc. Does Cypress support this type of configuration? If so; is there a reference design or IP package available?
Show LessSudheeshK_26 locked a discussion without actually answering a question. Why is that? Too many cases open to meet their performance goals?
Hello,
We have designed an FPGA board and now testing it. There are S71KS512SC0BHV00 MCP (HyperRam HyperFlash) and S70KS1281DPBHI02 HyperRam on it. We have successfully run S70KS1281DPBHI02 HyperRam at 150 Mhz but have some problems about S71KS512SC0BHV00 MCP. Now, we are trying to do memory test with HyperRam in MCP. We could do successfull transfers when clock is 50 Mhz and Burst size is 8. But when we increase the burst size (such as 16 or more) or clock rate ( such as 100 Mhz ), our test fails. The interesting thing is that the lower byte of 16 bit read data is always correct but higher byte is problamatic. Do you have any suggestions about this problem? I have two test boards and observe similar behaviour. By the way, we don't do any operation to HyperFlash in MCP. Drived CS#1 signal to logic '1'.
Best regards, Omer
Show LessHello,
Can we feed Hyperram's CK and CK# diffirential clock buses with SSTL18I io standard? I read that Hyperram's inputs and outputs are LV-CMOS compatible on datasheet.
Do we have to use LVCMOS18 io standart for clock buses with 1.8V devices?
Best Regards,
Emre
Show LessI implemented your HyperBus Memory Controller IP on several
technology. Now I am trying it on different technology. I have a issue and I
want to learn cause of problem. I configured the HyperBus Memory Controller IP
as compatible with HyperRAM over AXI register interface. There was not any
error for both read and write operation to IP registers. However IP does not
assert BVALID write response channel signal When I try to write to HyperRam
over AXI memory interface.Can you help me about this issue?.What could be cause
of this issue?
Can the hyperbus spec tolerate a 1ns delay in clock? My MCU only has a single ended clock output at 1.8v - I could use a pair of fast XOR gates to convert to psuedo differential. Has this been tried, is there a recommended way to do this? Will be running <100MHz for low power application.
Thanks.
Show Less