Hyper RAM Forum Discussions

I'm considering the S27KL0643/S27KS0643 memory part.

The microcontroller I am using is one of the newest STM32 parts, and I'm having trouble figuring out which variant of the memory I need. When creating the memory part number using the ordering information in the Cypress datasheet, the options are:

2 = 38-nm DRAM Process Technology- HyperBus

3 = 38-nm DRAM Process Technology- Octal

I'm still new to external RAM, so I am having trouble figuring out which variant I need.

The datasheet for the STM32 micro controller says this about the OCTOSPI interface:

The OCTOSPI supports most external serial memories such as serial PSRAMs, serial NAND and serial NOR Flash memories, HyperRAM™ and HyperFlash™ memories, with the following functional modes: • Indirect mode: all the operations are performed using the OCTOSPI registers. • Status polling-mode: the external memory status register is periodically read and an interrupt can be generated in case of flag setting. • Memory-mapped mode: the external memory is memory mapped and it is seen by the system as if it was an internal memory, supporting both read and write operations. The OCTOSPI supports the following protocols with associated frame formats: • the standard frame format with the command, address, alternate byte, dummy cycles and data phase • the HyperBus™ frame format

Hello,

I need a microcontroller that supports Hyperbus and Octal SPI to use HyperRAMs (S27KL0642 / S27KS0642, S27KL0643 / S27KS0643, S70KL1282 / S70KS1282, and S70KL1283 / S70KS1283).

Please let me which MCU you suggest?

Thank you,

Hi ,

Hi,

I am trying to compile the HyperBus Memory Controller IP - Release version V2L4_02  in a Xilinx Artix 7 FPGA device. I get a lot of timing errors. When digging in the design, I see a lot of the failing path that seems to be intended asynchronous as they are re-synchronized. My first guess is most of these timing path should be ignored during the timing analysis and set as false path.  I find it risky to set false path on these failing path as I am not familiar with the design and  I do not want to over-constraint and make Vivado ignore valid timing paths.

The sdc file provided with the IP-Core declares clock domains asynchronous between each others. But deeper in the design, clk and ip_clk domain are connected together in the file rpc2_ctrl_mem.v. By doing so, the 2 clock domains become a unique domain and therefore path between the 2 get analyzed.  I suspect that some unnecessary re synchronization logic should be removed on these path or false path constraints should be added.

As someone encountered such issue? Is it possible to find a list of what should be declared as false path?

Best Regards,

Alain

Hi,

Currently I am working on signal integrity analysis between Znyq 7020 and s27kl0642 HyperRam. For this purpose Which type of buffer can I use (hyperram pins connected to bank 34 lvcmos33 pins)?

According to AN211622 document I can not find max trace length of the any design?

For fpga design can you share any kind of topology (data,clock or address lines)?

Thanks for help.

Hi,

Currently I am working on signal integrity analysis of s27kl0642 model but I did not find ibis model.

https://www.cypress.com/ibis/s27kl0641-ibis?source=search&cat=software_tools

I can find only s27kl0641 but this model and my model is different.

Can you share ibis model of s27kl0642 with me?

Thanks for help.

Hi,

I need to S27KL0642GABHB020 ibis model for signal integrity analyisis?

I can not find your site.

Can you share with me S27KL0642GABHB020 ibis file?

Thanks for help.