Hyper RAM Forum Discussions
we have integrated S27KL0641DABHI023 HyperRAM with STM32L4R5ZI MCU . ( Circuit design is complete & PCB board in fabrication phase )
But while going through datasheet & application note of HyperRAM , I found following note
"The host must also leave the device enough time to perform these operations by keeping the length of the accesses it makes to a safe length .
The tCMS, CS# LOW maximum time, describes the maximum amount of time the host can access the device and still allow the self-refresh logic to operate.
tCMS ~ 4us. "
I am not getting how to fulfill this strange requirement of tCMS as main intention to use hyperram is to read/ write bulk amount of data in external ram .
Also how to calculate time required for each read write operation in program & break operating to respect tCMS timing . it is practically impossible task as most of the time data which need to be read / write is dynamic so cant predict whether operation time will exceed 4us or not .
Also situation becomes worst when Host MCU is operated with low frequency ( 8 , 16 MHz )
request you to please explain how to interface HyperRAM & program for bulk data read write .
Note : refer attached reference manual of Host MCU , section 19 Octo-SPI interface (OCTOSPI)
I am trying to bring up a board with HyperRAM memory solution (2x S70KS1281DPBHV02) . However I see read bit errors when running at 144MHz (but all works OK at 72MHz).
AN211622 says to match the length of RWDS to DQ +/-25mils.
Is this a real requirement? It seems a very tight constraint for a 144MHz bus.
The datasheet sets tDSS as +/-0.45ns - which still seems a tight requirement. However it is the same requirement all frequencies - so probably not related to my issue?
Does anybody know of a real reference design for HyperRAM?Show Less
’HyperBus Chipset Support’ にはXilinx Zynq7000でHyperRAMもHyperFLASHもサポートされると表示されています。