Hyper RAM Forum Discussions
Hi,
Currently I am working on signal integrity analysis of s27kl0642 model but I did not find ibis model.
https://www.cypress.com/ibis/s27kl0641-ibis?source=search&cat=software_tools
I can find only s27kl0641 but this model and my model is different.
Can you share ibis model of s27kl0642 with me?
Thanks for help.
Show LessHi,
I need to S27KL0642GABHB020 ibis model for signal integrity analyisis?
I can not find your site.
Can you share with me S27KL0642GABHB020 ibis file?
Thanks for help.
Show LessHello,
The answer to a prior discussion said that the iMX RT family supports both hyperram and hyperflash:
- i.Mx RT Platform Memory Recommendations
A few key questions remain.
1. Does imxrt1050 support combination devices such as S71KL256SC0BHB000?
1.1 Will a 166Mhz, 1.8V combination device become available in the future?
2. Does imrt1050 support both a hyperflash and a hyperram device on the same 8 bit FlexSPI bus?
2.1 Assuming so, will the combination degrade the performance of either?
3. Role of the RWDS signal, A_DQS in iMRT1050 documentation.
Hyperflash documentation describes RWDS as a read data strobe driven by the flash device.
Hyperram documentation describes RWDS as both a read strobe driven by the RAM and as a cycle timing signal and data mask driven by the processor.
But iMRT1050 documentation, reference manual chapter 27.4, table 27-4, describes the signal mainly as an input to the processor. Its function as an output does not seem compatible with section 3.3 of the HypeBus Specification, which describes the processor driving the signal as a data mask during write transactions.
Does the iMXRT1050 properly drive RWDS to operate HyperRAM with maximum throughput?
Thank you,
M.Reich
Show LessHello,
I need a microcontroller that supports Hyperbus to use HyperRAM 2 (64 and 128). Please let me know Arduino may be a good choice for this or you suggest another microcontroller?
Thank you,
Show LessWhat is the MTBF / FITs spec for this part: S27KS0641DPBHV020
It is mentioned that:
4. A Row is a group of words relevant to the internal memory array structure and additional latency may be inserted by RWDS when crossing Row boundaries - this is
device dependent behavior, refer to each HyperBus device data sheet for additional information. Also, the number of Rows may be used in the calculation of a
distributed refresh interval for HyperRAM memory.
5. A Page is a 16-word (32-byte) length and aligned unit of device internal read or write access and additional latency may be inserted by RWDS when crossing Page
boundaries - this is device dependent behavior, refer to each HyperBus device data sheet for additional information.
What value of latency to use when crossing pages or rows?
Is this the initial latency before RD data out? or it is extra latency between rows or pages?
like RD data as: [RD data of row1] [Latency] [RD data of row2]
Show LessHi,
I try to integrate the verilog model for S27ks0641 with the synopsys SSI IP.
I got the following:
Warning! Timing violation
$skew( negedge CSNeg:414195 PS, posedge CSNeg:498597 PS, 1 : 1 PS );
File: s27ks0641.v, line = 369
Scope: ssi_tbe.mem_model
Time: 498597 PS
I modified the value in the verilog file of tskew_CSNeg_CSNeg from 1 (tCSM) to 100000 to avoid it.
we run in 166MHz and the time between fall(CSNeg) and rise(CSNeg) can not be 1 ps
not sure why this value was set to such a short time?
the skew command requires a time interval of 1 ps max for CS to be active - that is not enough to deliver a Hyperbus frame.
can you please clarify?
Best wishes,
Cluny
Show LessHello,
Can we feed Hyperram's CK and CK# diffirential clock buses with SSTL18I io standard? I read that Hyperram's inputs and outputs are LV-CMOS compatible on datasheet.
Do we have to use LVCMOS18 io standart for clock buses with 1.8V devices?
Best Regards,
Emre
Show LessI implemented your HyperBus Memory Controller IP on several
technology. Now I am trying it on different technology. I have a issue and I
want to learn cause of problem. I configured the HyperBus Memory Controller IP
as compatible with HyperRAM over AXI register interface. There was not any
error for both read and write operation to IP registers. However IP does not
assert BVALID write response channel signal When I try to write to HyperRam
over AXI memory interface.Can you help me about this issue?.What could be cause
of this issue?