Hyper RAM Forum Discussions
您好，我确定我的上电初始化是按照数据手册给的时序，我的cs#和reset#都有上拉电阻，具体上电流程是这样的， 上电时序启动拉低reset#超过200ns ，并且cs#一直保持高电平，经过小于150us的时间再拉低cs#并且执行第一次写操作，您感觉我的上电初始化对吗？ 另一个问题想请教一下，关于自刷新我一直是忽略的，没有任何操作，没次进行读写操作的时候都是拉高cs#400ns左右然后开始进入传输C/A的状态，我现在读写数据只进行6个字节的传输，是不是我的cs#拉高的时间过过长呢。 最后一个问题，关于RWDS我这边现在的状态是上电就一直给的是高阻态，但是被从机那边拉高了所以只要是我给高阻态状态RWDS一直就是拉高的状态，这也是我怀疑上电初始化有问题的原因，但是现在我更感觉自刷新操作有很大的问题，希望您给一些关于自刷新延迟建议。主要没驱动起来的现象就是RWDS一直高电平状态，DQ一直是8’h01，希望尽快的得道您的回复，谢谢Show Less
Can the hyperbus spec tolerate a 1ns delay in clock? My MCU only has a single ended clock output at 1.8v - I could use a pair of fast XOR gates to convert to psuedo differential. Has this been tried, is there a recommended way to do this? Will be running <100MHz for low power application.
Could you tell me the difference between S27KS0641 and S27KS0642 ? What should be changed when migrating from S27KS0641 to S27KS0642 ?
Thanks and regards.
I'm requesting the IBIS file for the S70KS1281. Temporarily, a modification of the S27KS0641 can get me by but I hope the S70KS1281 IBIS file will be available soon.Show Less
I am looking for a future growth plan for the HyperRAM parts. What sizes and when they will be available. The current 128mbit parts do not meet our needs but they would if there was a 256mbit part.
I see the diagrams and discussions about connecting multiple slave hyperrams to a master. is it possible to do that with the two slaves being in parallel instead of separately accessed? the same controls and address commands but reads and writes would be 16 bit effective data.
Dear Support team ,
Thia is with reference to past discussion with Takahiro . tCMS timing restriction (refresh interval) implementation in Host MCU
We have successfully integrated S27KL0641DABHI023 HyperRAM with STM32L4R5ZI MCU and able to read & write data .
but for some frequency setting we are getting garbage data from HyperRAM for first two bytes .
please refer attached document having details of 3 test case ( case no 3 having issue of first two bytes garbage )