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Hyper RAM Forum Discussions

Hyper RAM Forum Discussions

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user_4409276
Hyper RAM
您好,我确定我的上电初始化是按照数据手册给的时序,我的cs#和reset#都有上拉电阻,具体上电流程是这样的, 上电时序启动拉低reset#超过200ns ,并且cs#一直保持高电平,经过小于150us的时间再拉低cs#并且执行第一次写操作,您感觉我的上电初始化对吗? 另一个问题想请教一下,关于自刷... Show More
user_4409276
Hyper RAM

对于hyper ram的上电初始化有疑问,我怀疑我一直没有驱动起来这个memory,因为从hyper  ram 发出的rwds 一直为高电平吧,并且DQ一直是8’h01,希望尽快得到您的帮助

BeCr_3107286
Hyper RAM
Can the hyperbus spec tolerate a 1ns delay in clock? My MCU only has a single ended clock output at 1.8v - I could use a pair of fast XOR gates to con... Show More
GrWa_2302706
Hyper RAM
KS0641 ibis
Solved

Hi

Sade_4357781
Hyper RAM

I am looking for Thermal Resistance and Temperature Junciton Max...

Thanks!

GrWa_2302706
Hyper RAM
HiCould you tell me the difference between S27KS0641 and S27KS0642 ? What should be changed when migrating from S27KS0641 to S27KS0642 ?Thanks and reg... Show More
toduc_677646
Hyper RAM
I'm requesting the IBIS file for the S70KS1281. Temporarily, a modification of the S27KS0641 can get me by but I hope the S70KS1281 IBIS file will be ... Show More
jobr_4199181
Hyper RAM
I am looking for a future growth plan for the HyperRAM parts.  What sizes and when they will be available.  The current 128mbit parts do not meet our ... Show More
jobr_4199181
Hyper RAM
I see the diagrams and discussions about connecting multiple slave hyperrams to a master.  is it possible to do that with the two slaves being in para... Show More
Anonymous
Hyper RAM
Dear Support team ,Thia is with reference to past discussion with Takahiro . tCMS timing restriction (refresh interval) implementation in Host MCU We ... Show More
Forum Information

Hyper RAM

HyperRAM™ memory Forum discusses self-refresh DRAM operating on the 12-pin HyperBus interface. With a read throughput up to 333 MB/s, the HyperRAM for SoCs with limited on-board RAM providing external scratch-pad memory for fast read and write operations.