Hi,

In order to communicate with the memory Hyper RAM S27KL0642 I use a NUCLEO-L4R5ZI board.

My problem is that the frequency that can be generated by the MCU is 120MHz and in the datasheet of the memory componment's operation is only detailled for two frequencies (200 and 166MHz).

My question is, does the memory would properly work at 120MHz frequency? If so, are timing specifications the same?

Kind regards

We are considering incorporating the Hyper-RAM S27KS0642GABHV020 (and later the 128-Mbit counterpart) as the DRAM solution in our upcoming product design. The IC will be clocked at 150 MHz. In each transaction, we would like to store/read data in 1024 KB chunks, using Linear Burst Mode (essentially each transaction will read/write a row). Beside the Tcsm limitation, which limits each transaction to 600 cycles when using 150 MHz clock, is there a limit to the number of bytes that can be read or written in a transaction when using Linear Burst Mode? Is our use-case, which requires 527 cycles and respects Tcsm, viable?

Kind regards,
DM_Y

This isn't a HyperRAM question in particular, but this seems like the best place to post this.  I am working on a Xilinx FPGA design that is interfacing with an STM32H microcontroller.  We were hoping to operate in HyperBus mode (which the microcontroller supports), but with the FPGA as the slave.  I know from this thread that Cypress did not supply a slave version of their IP core in 2019, but I was hoping that that might have changed by now: https://community.cypress.com/t5/Hyper-RAM/Using-an-FPGA-as-a-HyperBus-slave/m-p/136850#M84

It appears to me that the only way forward is to design a core by hand, but I was hoping to avoid that if possible.

Is it possible to convert the Verilog S27KkL0642.v Model into a netlist?

I have been using the S27KL0642.v model very successfully with the Intel Starter ModelSim Simulator.  However, my design has grown to the point that it is very painfully slow.  My design is entirely written in VHDL except for the s27KL0642.v Model.  I also have a copy of Modelsim PE with a VHDL License which run much faster.  I am wondering if I can get a universal netlist version of the S27KL0642 Model that would allow me to use my copy of ModelSim PE with the VHDL License to simulate my design using the netlist version of the S27KL0642 Model instead of the Verilog version??????????????????????

In studying the Hyper Ram Bus Specifications and the timing of the bus signals specifically the relationship between RWDS and the 8 Data bits, I am not sure how to reliably clock the read data into my Intel/Altera FPGA.  I occurs to me that what is needed is a 3 or 4 ns delay line or a 90 degree phase shift to delay the RWDS strobe until the data is stable.  

It is evident that this problem can be solved by the availability of Hyper Ram Controllers.  Is there any available information on how this is typically accomplished???

Thanks,

Bill

I am looking for a Verilog or VHDL Simulation Model for a Hyperram memory device.  Does it exist?  I am using the IS66WVH16M8ALL-166B1LI device, but any Hyperram Simulation Model will work for my purposes.

Thanks,

William Sheppard

wdsheppard@earthlink.net

How many mixed of HyperRAM / HyperFlash can exist on the same bus? What are the limitations and critical points?

e.g.

2x HyperRAM  + 1 x HyperFlash

1x HyperRAM  + 2 x HyperFlash

Thx.

I working on some hardware that will use the S70K HyperRAM.

The hardware guide for HyperRAM, where it talks about layout requirements and such, makes a vague reference to using terminations if required. I don't have access to signal integrity tools so I have no way of knowing if the termination resistors will be required or not. My board will be pretty small (less than 1" x 2"), so I will place the RAM as close to the MCU as physically possible.

One of the demo kits for a microcontroller I am considering (STM32H7 variant) places series resistors at the HyperRAM pins only. As the data pins are bidirectional, I'm not sure why the terminations would only be needed in one direction (in this case RAM->MCU but not MCU->RAM).

Does anyone have any advice?