Hyper RAM Forum Discussions

There is an error in the DCARS footprint in the S70KS1282GABHB03 datasheet.

https://www.infineon.com/cms/en/search.html#!term=S70KS1282GABHB03&view=all

https://www.infineon.com/dgdl/Infineon-S70KL1282_S70KS1282_3.0_V_1.8_V_128_Mb_(16_MB)_HYPERBUS_INTERFACE_HYPERRAM_(SELF-REFRESH_DRAM)-DataSheet-v03_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ee9315b7210

Section 12.2, Figure 37. The *DCARS*-capable part should have signals PSC and PSC# on pins B5 and C5, respectively. Those signals are not shown.

Can you please confirm that the footprint is wrong so that we can proceed forward with our board fabrication?

In the past we have used the 64Mbit DCARS-capable part which has the correct DCARS footprint pinout shown with the PSC/PSC# signals. We just want to make certain that the footprint is in error and that the PSC/PSC# pins are where we think they are.

Why are there no HyperRAM parts with the DCARS feature in higher densities like 512Mbit?

The highest density hyperram with DCARS feature that I can find is 128Mbit.

The hyperram parts with the DCARS feature are a superior product in my opinion. Will higher density HyperRAMs w/ DCARS be released soon?

Hello I'm looking for a verilog simulation model for the S70KL1281 (Hyper Ram).
Could you please point me the link to download it? (Prefer the model can be supported by xcelium and questasim)

** Note ** : I have been using the one provided in public (s27kl0642), but there is something more specific I would like to confirm with the exact variant in S70KL1281. Hope Infineon support team can help me with this.

Thanks a lot!

Regards,
SY

I was looking at the product page for the S80KS5122GABHA023. On the FAQ it states the following:

In Asynchronous SRAMs, the address pins (Ax) can be assigned in any bit order. For instance, pin A15 of CPU can be connected to A0 of SRAM, A10 of CPU to A1 of SRAM etc. Address assignment can be made as dictated by layout or other board-level constraints; there is no restriction from the internal SRAM-addressing standpoint, unless otherwise specified in the datasheet.
Likewise, data lines can be assigned in any order, within a specific byte. For instance, D0 of CPU can be connected to D4 of SRAM, D1 of CPU to D6 of SRAM etc. However, the data bit assignment should not cross byte boundaries if byte level accesses are made. For instance, a higher bit data of CPU connected to lower bit data line in SRAM could result in conflict when performing byte-specific (lower byte or higher byte) accesses. If such individual byte-level accesses are not made, routing can extend beyond byte boundaries also.

Does this actually apply to HyperRAM such as the S80KS5122, is the FAQ just some generic FAQ that gets placed on all the pages? Could anyone provide some info about how this could be implemented on the HyperRAM? Can I just connect any data line to any pin on the MCU? I'm still new to HyperRAM so I am confused about this.

Hyper bus recognizes octal interfaces as standardized, is they compatible?

Can I put Hyper bus interface memory on an SoC that supports octal interfaces?

Hi,
I have a TE0890 FPGA board (or S7 mini). There is Xilinx Spartan-7 and 64 Mbit HyperRAM. I want to use this HyperRAM so I need to HyperBus Controller IP but I cannot find it. Can anyone help me how can I find that IP?
Thanks,
Recep

When migrating from S27KS0641 to S27KS0642, in the attached PDF
On the 3rd page, it says "From a hardware point of view, no changes to the PCB are required."
S27KS0641 requires "differential clock", S27KS0642 "differential clock is optional", and "When CK# of S27KL0642 is not used,
Can be left floating. ”, there is a difference in the PIN specifications.

Therefore, the items to be confirmed are that the current board that uses the S27KS0641 is designed with a differential clock connected based on the ["HyperFlash™ and HyperRAM™ layout guide.pdf".] Is there any problem if I migrate (replace) to S27KS0642 without changing PCB?

Dears，

Can we provide these parameters about S27KL0642DPBHB020 

Thermal Resistance Tj，θJB

Thanks.