Hyper RAM Forum Discussions
we are using two S27KS0642 as ping-pong buffers for a USB3 application (commercial temperature)
We will be driving them to their performance limits (so the full 3.2Gbit/s).
In order to achieve the maximum performance and reduce complexity we would like to violate the Tcsm.
(I understand, that this should be possible as long as we ensure the refresh of all cells)
Our major scenario will be the following:
1. Write the complete memory
2. Read the complete memory within 40ms maximum
3. (Possibly) read the complete memory again within 40ms maximum
As far as I understand the behavior of the memory it should be fine to violate Tcsm as long as we ensure, that the complete memory is read/written within 64ms.
Am I correct with that assumption or are there any problems to expect?
We have a second scenario (USB2.0/1.0 fallback) that will be:
1. Write the complete memory (ignoring Tcsm)
2. Read the complete memory in smaller junks honoring Tcsm
I would assume, that writing the complete memory will cause a complete refresh and that afterwards the self refresh operation will start running as before?
I'd like to check and use for my test board using hyperRAM solution.
Can I get full datasheet of S71KS512SC and S27KS1281DPBHA02?
Thank youShow Less
I am testing the S27KS0642GABHI020 on our board with Lattice crosslink-NX FPGA. I have 2 hyperbus controllers to use, one is the cypress hyperbus 2.0 controller and the other is a much simpler one from Lattice. I firstly tried the one from Lattice, I found no matter what I wrote into address 0 I always read back random data, even I didn't write. To avoid the wrong initial latency issue, I looked at the incoming data waveform from Lattice Radiant Reveal logic analyzer, they are always random data (mostly 8'h15). I also probed pins with scope to confirm data is coming from HyperRam. HyperRAM is running at 60MHz, but I also tried as low as 24MHz or higher at 120MHz, all similar results on reading.
What should I check? I also tried manual reset for Hyperram after power up.
Can someone please direct me as to where I can find an .ibis model for the S27KL0641DABHI020. I would like to simulate the design I am working on that includes this IC as the memory component.Show Less
In order to communicate with the memory Hyper RAM S27KL0642 I use a NUCLEO-L4R5ZI board.
My problem is that the frequency that can be generated by the MCU is 120MHz and in the datasheet of the memory componment's operation is only detailled for two frequencies (200 and 166MHz).
My question is, does the memory would properly work at 120MHz frequency? If so, are timing specifications the same?
Kind regardsShow Less
We are considering incorporating the Hyper-RAM S27KS0642GABHV020 (and later the 128-Mbit counterpart) as the DRAM solution in our upcoming product design. The IC will be clocked at 150 MHz. In each transaction, we would like to store/read data in 1024 KB chunks, using Linear Burst Mode (essentially each transaction will read/write a row). Beside the Tcsm limitation, which limits each transaction to 600 cycles when using 150 MHz clock, is there a limit to the number of bytes that can be read or written in a transaction when using Linear Burst Mode? Is our use-case, which requires 527 cycles and respects Tcsm, viable?
This isn't a HyperRAM question in particular, but this seems like the best place to post this. I am working on a Xilinx FPGA design that is interfacing with an STM32H microcontroller. We were hoping to operate in HyperBus mode (which the microcontroller supports), but with the FPGA as the slave. I know from this thread that Cypress did not supply a slave version of their IP core in 2019, but I was hoping that that might have changed by now: https://community.cypress.com/t5/Hyper-RAM/Using-an-FPGA-as-a-HyperBus-slave/m-p/136850#M84
It appears to me that the only way forward is to design a core by hand, but I was hoping to avoid that if possible.Show Less
Is it possible to convert the Verilog S27KkL0642.v Model into a netlist?
I have been using the S27KL0642.v model very successfully with the Intel Starter ModelSim Simulator. However, my design has grown to the point that it is very painfully slow. My design is entirely written in VHDL except for the s27KL0642.v Model. I also have a copy of Modelsim PE with a VHDL License which run much faster. I am wondering if I can get a universal netlist version of the S27KL0642 Model that would allow me to use my copy of ModelSim PE with the VHDL License to simulate my design using the netlist version of the S27KL0642 Model instead of the Verilog version??????????????????????Show Less