Hyper RAM Forum Discussions

I implemented your HyperBus Memory Controller IP on several
technology. Now I am trying it on different technology. I have a issue and I
want to learn cause of problem. I configured the HyperBus Memory Controller IP
as compatible with HyperRAM over AXI register interface. There was not any
error for both read and write operation to IP registers. However IP does not
assert BVALID write response channel signal When I try to write to HyperRam
over AXI memory interface.Can you help me about this issue?.What could be cause
of this issue?

Can the hyperbus spec tolerate a 1ns delay in clock? My MCU only has a single ended clock output at 1.8v - I could use a pair of fast XOR gates to convert to psuedo differential. Has this been tried, is there a recommended way to do this? Will be running <100MHz for low power application.

Thanks.

Hi

Could you tell me the difference between S27KS0641 and S27KS0642 ? What should be changed when migrating from S27KS0641 to S27KS0642 ?

Thanks and regards.

Grace

I am looking for a future growth plan for the HyperRAM parts.  What sizes and when they will be available.  The current 128mbit parts do not meet our needs but they would if there was a 256mbit part.

Thanks

Joe

I see the diagrams and discussions about connecting multiple slave hyperrams to a master.  is it possible to do that with the two slaves being in parallel instead of separately accessed?  the same controls and address commands but reads and writes would be 16 bit effective data.

Thanks

Dear Support team ,

Thia is with reference to past discussion with Takahiro . tCMS timing restriction (refresh interval) implementation in Host MCU

We have successfully integrated S27KL0641DABHI023 HyperRAM with STM32L4R5ZI  MCU  and able to read & write  data .

but for some frequency setting we are getting garbage data from HyperRAM for first two bytes .

please refer attached document having details of 3 test case  ( case no 3 having issue of first two bytes garbage )

Thanks,

Gaurav

Hi,

   I am looking for a Static-RAM kind of device that can meet our performance, space and power requirements. Our requirements are;

1. Random read bandwidth of about 150 MB per sec for burst read size of 1
2. about 50mA current at 1.8V (or 2.5V)
3. smallest area like 8mmx8mm or something similar
4. ambient temperature of -40C to +105C
5. Minimum density of 8Mbits or more

I have quickly gone through your hyperRAM devices but I could NOT find bandwidth number for truly random access read. Most of our read will be of burst size 1. Our application will first write data to the hyperRAM and then it will perform random read operations (no switching between write and read operations constantly).

1. If the internal hyperRAM's DDR needs a refresh, what would be the worst case read time?

2. What is the worst case bandwidth for truly random read access?

3. Does not switching between read and write but just keep doing random read only make Read-Write-Recovery time (tRWR) zero?

4. If you have any recommendation for sync or async SRAM devies that could meet our requirements, please recommend us.

Thanks for your time and help.