Hyper RAM

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FG_16199511
Hyper RAM
We are looking for a way to integrate external RAM (possibly as large as 16MB) in our Project. Right now, we can only use Quad-SPI to connect the RAM-... Show More
Berkj
Hyper RAM
Hello everyone, I asked the same question under HyperFlash board; however, this applies to the HyperRAM too since they follow the HyperBus timing spec... Show More
GoKo_4683011
Hyper RAM
Hello, We are using the STM32L4R5 (Nucleo-144, L4R5ZI-P) to implement HyperRAM memory (S27KL0642) under hyperbus protocol. There is a problem between ... Show More
berniwa
Hyper RAM
Hi, we are using two S27KS0642 as ping-pong buffers for a USB3 application (commercial temperature) We will be driving them to their performance limit... Show More
Stark38
Hyper RAM
Hi, I'm trying to implement Hyperbus protocol for Hyper RAM on a NUCLEOL4R5ZI-P without success. Is some exemple on STM32L4R are available?   Kind reg... Show More
ToIk_1341346
Hyper RAM

レジスタをRDする際にデーターシートではレイテンシなしと理解したのですが、

シミュレーションモデルではレイテンシがあるようです。

ここの仕様はどのようになっているのでしょうか?

pf_arc
Hyper RAM
We are using a Cypress/Infineon HyperRAM, part number S70KS1281DPBHV020, driven by the Cypress/Infineon Hyperbus Controller on a Xilinx FPGA (xc7k160t... Show More
KYUNGHYUN
Hyper RAM
Hello   I'd like to check and use for my test board using hyperRAM solution. Can I get full datasheet of S71KS512SC and S27KS1281DPBHA02?   Thank you Show More
johnsonlee0805
Hyper RAM
Hi, I am testing the S27KS0642GABHI020 on our board with Lattice crosslink-NX FPGA. I have 2 hyperbus controllers to use, one is the cypress hyperbus ... Show More
MariaWohlsdorf
Hyper RAM
Can someone please direct me as to where I can find an .ibis model for the S27KL0641DABHI020.  I would like to simulate the design I am working on tha... Show More
Board Information

Hyper RAM

HyperRAM™ memory Forum discusses self-refresh DRAM operating on the 12-pin HyperBus interface. With a read throughput up to 333 MB/s, the HyperRAM for SoCs with limited on-board RAM providing external scratch-pad memory for fast read and write operations.
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