Hello,

I am looking for advice in using an Infineon S27KS0642 64Mb HyperRAM chip on a STM32L4R5Z and configured via CUBE.

I have it working, so I am pretty sure that the hardware is connected correctly and I can read and write successfully to it.  However, if I leave it for a while and then read again, the stored data is being corrupted (usually just single bits) and it gradually gets worse, as if the refresh isn’t working correctly.

My OctoSPI init function is shown below and I have a Peripheral SPI clock of 120Mhz.  Any advice would be very welcome.

Thanks

/* OCTOSPI1 init function */

void MX_OCTOSPI1_Init(void)

{

  /* USER CODE BEGIN OCTOSPI1_Init 0 */

    // release the beast...

    HAL_GPIO_WritePin(RAM_RST_GPIO_Port, RAM_RST_Pin, GPIO_PIN_RESET);

    HAL_GPIO_WritePin(RAM_RST_GPIO_Port, RAM_RST_Pin, GPIO_PIN_SET);

  /* USER CODE END OCTOSPI1_Init 0 */

  OSPIM_CfgTypeDef OSPIM_Cfg_Struct = {0};

  OSPI_HyperbusCfgTypeDef sHyperBusCfg = {0};

  /* USER CODE BEGIN OCTOSPI1_Init 1 */

  /* USER CODE END OCTOSPI1_Init 1 */

  hospi1.Instance = OCTOSPI1;

  hospi1.Init.FifoThreshold = 1;

  hospi1.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE;

  hospi1.Init.MemoryType = HAL_OSPI_MEMTYPE_HYPERBUS;

  hospi1.Init.DeviceSize = 23;

  hospi1.Init.ChipSelectHighTime = 7;

  hospi1.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE;

  hospi1.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0;

  hospi1.Init.ClockPrescaler = 3;

  hospi1.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE;

  hospi1.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE;

  hospi1.Init.ChipSelectBoundary = 0;

  hospi1.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED;

  if (HAL_OSPI_Init(&hospi1) != HAL_OK)

  {

    Error_Handler();

  }

  OSPIM_Cfg_Struct.ClkPort = 1;

  OSPIM_Cfg_Struct.DQSPort = 1;

  OSPIM_Cfg_Struct.NCSPort = 1;

  OSPIM_Cfg_Struct.IOLowPort = HAL_OSPIM_IOPORT_1_LOW;

  OSPIM_Cfg_Struct.IOHighPort = HAL_OSPIM_IOPORT_1_HIGH;

  if (HAL_OSPIM_Config(&hospi1, &OSPIM_Cfg_Struct, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)

  {

    Error_Handler();

  }

  sHyperBusCfg.RWRecoveryTime = 7;

  sHyperBusCfg.AccessTime = 7;

  sHyperBusCfg.WriteZeroLatency = HAL_OSPI_LATENCY_ON_WRITE;

  sHyperBusCfg.LatencyMode = HAL_OSPI_FIXED_LATENCY;

  if (HAL_OSPI_HyperbusCfg(&hospi1, &sHyperBusCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)

  {

    Error_Handler();

  }

  /* USER CODE BEGIN OCTOSPI1_Init 2 */

    OSPI_HyperbusCmdTypeDef      sCommand = {0};

    OSPI_MemoryMappedTypeDef     sMemMappedCfg = {0};

    // Memory-mapped mode configuration

    sCommand.AddressSpace           = HAL_OSPI_MEMORY_ADDRESS_SPACE;

    sCommand.AddressSize            = HAL_OSPI_ADDRESS_32_BITS;

    sCommand.DQSMode                = HAL_OSPI_DQS_ENABLE;

    sCommand.Address                = 0;

    sCommand.NbData                 = 1;

    if (HAL_OSPI_HyperbusCmd(&hospi1, &sCommand, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK)

     {

     Error_Handler();

     }

    sMemMappedCfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_DISABLE;

    //sMemMappedCfg.TimeOutActivation = HAL_OSPI_TIMEOUT_COUNTER_ENABLE;

    sMemMappedCfg.TimeOutPeriod     = 1;

    if (HAL_OSPI_MemoryMapped(&hospi1, &sMemMappedCfg) != HAL_OK)

     {

     Error_Handler();

     }

  /* USER CODE END OCTOSPI1_Init 2 */

}

Hi,

In our design we want to connect a Hyperam S27KS0643GABHV020 to FlexIO port1 of NXP Processor RT1176.

Can you please share if there are any test result details of this interface is already validated?

Can we use this hyperam at 166MHz with single ended clock at 3.0V operation? 

Regards

Abhishek 

On HyperBUS specification it is shown that slave devices can be paralleled on the same bus however in e.g. HyperRAM layout guidelines there is no guideline on any routing topology when paralleling memories on the same bus.

What are the guidelines for routing paralleled memories? Signals should be routed in T-shape, Y-shape etc. or does it matter? Can we route paralleled memories in a way that from master the bus is routed to first memory and from the first memory the bus will continue to second memory? Or should we ensure that the bus routing length to both memories will be as close as possible each other (from Master)?

Datasheet Info :

Name – S80KS5122  512 Mb: HYPERRAM™ self-refresh dynamic RAM (DRAM) with HYPERBUS™ interface 1.8 V

Revision - 002-31338 Rev. *B

Date – 2021-09-27

Calculating addresses from Datasheet, we are getting below address:

Identification Register 0 Read – Die 1 :- 400000h

Identification Register 1 Read – Die 1 :- 400001h

Configuration Register 0 Read – Die 1 :- 400800h

Configuration Register 1 Read – Die 1 :- 400801h

Die 0 Address Range :  [0h, FFFFFFh]

Die 1 Address Range :  [1000000h, 1FFFFFFh]

Doubt :- Above mentioned 4 register’s address lies in Die 0 address range but registers are used for Die 1. Can you please confirm what are the correct values ?

Our expected address values are given below:

Identification Register 0 Read – Die 1 :-  1000000h

Identification Register 1 Read – Die 1 :-   1000001h

Configuration Register 0 Read – Die 1 :-  1000800h

Configuration Register 1 Read – Die 1 :-  1000801h

System Address[26:19] and CA Bits [39:32] -   20h

Hello,
we had to replace the S70KL1281 with the S70KL1283 due to availability. Unfortunately that did not work. Now we have seen in the data sheet that for the S70KL1282 "hyperbus" is specified and for the S70KL1283 "octal". Just to be sure: Does this mean that the S70KL1283 does not support hyperbus?
We use the memory with a STM32H7 and have tried to adapt the software (without hyperbus). But that did not work properly either. Are there any examples of use, or hints on how to make the settings.

Thanks!

Are there any Hyper RAM devices that can withstand 5+ krad?

If not, are there similar devices that would be recommended?  I need:

- 256Mb+

- 200MHz+

- 1.8V

- Small package (currently use 6x8mm BGA and 2.18x2.76mm die

Thank you!

I have a question about the RWDS timing during the CA interval where simulation disagrees with the datasheet.

The simulation shows a HyperRAM write cycle where a refresh collision has occurred. RWDS changes in the middle of the CA interval signaling 2x latency. The datasheet only shows RWDS valid on CS# low.

If it is important to know when RWDS should be sampled to guarantee proper latency.

Infineon S27KS0642 1.8V 64Mb 200MHz
S27KS0642GABHI020

Clock is 125MHz. Initial latency set to 5. Variable latency enabled

Infineon memory model with the correct `define selected