We are considering incorporating the Hyper-RAM S27KS0642GABHV020 (and later the 128-Mbit counterpart) as the DRAM solution in our upcoming product design. The IC will be clocked at 150 MHz. In each transaction, we would like to store/read data in 1024 KB chunks, using Linear Burst Mode (essentially each transaction will read/write a row). Beside the Tcsm limitation, which limits each transaction to 600 cycles when using 150 MHz clock, is there a limit to the number of bytes that can be read or written in a transaction when using Linear Burst Mode? Is our use-case, which requires 527 cycles and respects Tcsm, viable?
Kind regards,
DM_Y
