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Hyper RAM

DM_Y
New Contributor

We are considering incorporating the Hyper-RAM S27KS0642GABHV020 (and later the 128-Mbit counterpart) as the DRAM solution in our upcoming product design. The IC will be clocked at 150 MHz. In each transaction, we would like to store/read data in 1024 KB chunks, using Linear Burst Mode (essentially each transaction will read/write a row). Beside the Tcsm limitation, which limits each transaction to 600 cycles when using 150 MHz clock, is there a limit to the number of bytes that can be read or written in a transaction when using Linear Burst Mode? Is our use-case, which requires 527 cycles and respects Tcsm, viable?

Kind regards,
DM_Y

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1 Solution
PradiptaB_11
Moderator
Moderator

Hi,

There is no limitation to the number of bytes that that can read/written using linear burst mode. Your use case is viable. You can also use our Verilog model to verify this.

Thanks,

Pradipta.

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2 Replies
PradiptaB_11
Moderator
Moderator

Hi,

There is no limitation to the number of bytes that that can read/written using linear burst mode. Your use case is viable. You can also use our Verilog model to verify this.

Thanks,

Pradipta.

View solution in original post

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DM_Y
New Contributor

Thank you for your reply, that is great! The reason we were confused was because on page 13 of the datasheet, in section Write Transactions (Memory Array Write), it states that:


Because the master is driving RWDS during write data transfers, neither the master nor the HyperRAM device are able to indicate a need for latency within the data transfer portion of a write transaction.
The acceptable write data burst length setting is also shown in configuration register 0.

So after reading that it was not clear if there is a burst size limit in a write transaction using Linear Burst Mode.

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