HI,
Yes no problem!
void ospi_config(void)
{
//OCTOSPI IO Manager clock enable
RCC->AHB3ENR |= RCC_AHB3ENR_OSPI1EN;
//OCTOSPI1 clock enable
RCC->AHB2ENR |= RCC_AHB2ENR_OSPIMEN;
//CR REGISTER
//OCTOSPI1 enable
OCTOSPI1->CR |= OCTOSPI_CR_EN;
//INDIRECT write
OCTOSPI1->CR |= (0 << OCTOSPI_CR_FMODE_Pos);
OCTOSPI1->CR |= (5 << OCTOSPI_CR_FTHRES_Pos);
//DCR1 REGISTER
//REGISTER SPACE
OCTOSPI1->DCR1 |= (5 << OCTOSPI_DCR1_MTYP_Pos);
//DEVICE SIZE = 26
OCTOSPI1->DCR1 |= (0x1A << OCTOSPI_DCR1_DEVSIZE_Pos);
//CHIPSELECT HIGH TIME = 1cycle
OCTOSPI1->DCR1 |= (0 << OCTOSPI_DCR1_CSHT_Pos);
//DELAYBLOCK NOT BYPASSED
OCTOSPI1->DCR1 |= (0 << OCTOSPI_DCR1_DLYBYP_Pos );
//FREERUNING CLOCK DISABLED
OCTOSPI1->DCR1 |= (0 << OCTOSPI_DCR1_FRCK_Pos);
//CLOCK MODE = LOW
OCTOSPI1->DCR1 |= (0 << OCTOSPI_DCR1_CKMODE_Pos);
//DCR2 REGISTER
//CLOCK PRESCALER = 3
OCTOSPI1->DCR2 |= (2 << OCTOSPI_DCR2_PRESCALER_Pos);
/****** CCR REGISTER ******/
//INSTRUCTION SENT ON EVERY TRANSACTION
OCTOSPI1->CCR |= (0 << OCTOSPI_CCR_SIOO_Pos);
//DQS Enable
OCTOSPI1->CCR |= OCTOSPI_CCR_DQSE;
// DDTR enable
OCTOSPI1->CCR |= OCTOSPI_CCR_DDTR;
//DATA on a single line
OCTOSPI1->CCR |= OCTOSPI_CCR_DMODE_0;
//16-bytes Address size
OCTOSPI1->CCR |= OCTOSPI_CCR_ADSIZE_0;
//Address DTR enable
OCTOSPI1->CCR |= OCTOSPI_CCR_ADDTR;
//Address on a single line
OCTOSPI1->CCR |= OCTOSPI_CCR_ADMODE_0;
//DHQC enable
/***** TCR REGISTER *****/
OCTOSPI1->TCR |= OCTOSPI_TCR_DHQC;
//5 dummy cycles
OCTOSPI1->TCR |= (5 << 0);
/***** WTCR REGISTER *****/
//5 dummy cycles in write operation
OCTOSPI1->WTCR |= (5 << 0);
/***** WCCR REGISTER *****/
OCTOSPI1->WCCR |= OCTOSPI_WCCR_DQSE;
//DSQ Enable
OCTOSPI1->WCCR |= (OCTOSPI_WCCR_DQSE);
//DDTR Enable
OCTOSPI1->WCCR |= (OCTOSPI_WCCR_DDTR);
//Data on single line
OCTOSPI1->WCCR |= (OCTOSPI_WCCR_DMODE_2) ;
OCTOSPI1->WCCR |= (OCTOSPI_WCCR_ADSIZE_0);
OCTOSPI1->WCCR |= (OCTOSPI_WCCR_ADDTR);
OCTOSPI1->WCCR |= (OCTOSPI_WCCR_ADMODE_0);
/***** HCLR ******/
// Trwr = 4 clk
OCTOSPI1->HLCR |= (4 << OCTOSPI_HLCR_TRWR_Pos);
//Tacc = 4 clk
OCTOSPI1->HLCR |= (4 << OCTOSPI_HLCR_TACC_Pos);
//Variable latency
OCTOSPI1->HLCR |= (0 << OCTOSPI_HLCR_LM_Pos);
}
void ospi1_write_reg(uint32_t tdata, uint32_t add)
{
//INDIRECT write
OCTOSPI1->CR |= (0 << OCTOSPI_CR_FMODE_Pos);
//REGISTER SPACE + HYPERBUS
OCTOSPI1->DCR1 |= (5 << OCTOSPI_DCR1_MTYP_Pos);
OCTOSPI1->AR = add;
OCTOSPI1->DR |= tdata;
OCTOSPI1->DLR = 4;
while( ((OCTOSPI1->SR & OCTOSPI_SR_BUSY_Msk) >> OCTOSPI_SR_BUSY_Pos == 1))
{
HAL_Delay(1);
}
if(((OCTOSPI1->SR & OCTOSPI_SR_TCF_Msk ) >> OCTOSPI_SR_TCF_Pos) == 1 )
{
OCTOSPI1->FCR |= OCTOSPI_FCR_CTCF;
}
}
void ospi1_read_reg(uint32_t add)
{
OCTOSPI1->AR = 0x00010000;
//INDIRECT Read MODE
OCTOSPI1->CR |= (1 << OCTOSPI_CR_FMODE_Pos);
//REGISTER SPACE
OCTOSPI1->CCR |= (0 << OCTOSPI_CCR_SIOO_Pos);
//DQS Enable
OCTOSPI1->CCR |= OCTOSPI_CCR_DQSE;
// DDTR enable
OCTOSPI1->CCR |= OCTOSPI_CCR_DDTR;
//DATA on a single line
OCTOSPI1->CCR |= (0 << OCTOSPI_CCR_DMODE_Pos);
// OCTOSPI1->CCR |= OCTOSPI_CCR_ABMODE_0;
//16-bytes Address size
OCTOSPI1->CCR |= OCTOSPI_CCR_ADSIZE_0;
//Address DTR enable
OCTOSPI1->CCR |= OCTOSPI_CCR_ADDTR;
//Address on a single line
OCTOSPI1->CCR |= OCTOSPI_CCR_ADMODE_0;
while( ((OCTOSPI1->SR & OCTOSPI_SR_BUSY_Msk) >> OCTOSPI_SR_BUSY_Pos == 1))
{
}
if(((OCTOSPI1->SR & OCTOSPI_SR_TCF_Msk ) >> OCTOSPI_SR_TCF_Pos) == 1 )
{
OCTOSPI1->FCR |= OCTOSPI_FCR_CTCF;
}
pData = OCTOSPI1->DR;
}
Thank you!
