Hyperram self-refresh

[berniwa]

Hi,

we are using two S27KS0642 as ping-pong buffers for a USB3 application (commercial temperature)

We will be driving them to their performance limits (so the full 3.2Gbit/s).
In order to achieve the maximum performance and reduce complexity we would like to violate the Tcsm.
(I understand, that this should be possible as long as we ensure the refresh of all cells)

Our major scenario will be the following: 
1. Write the complete memory
2. Read the complete memory within 40ms maximum
3. (Possibly) read the complete memory again within 40ms maximum

As far as I understand the behavior of the memory it should be fine to violate Tcsm as long as we ensure, that the complete memory is read/written within 64ms. 

Am I correct with that assumption or are there any problems to expect?

We have a second scenario (USB2.0/1.0 fallback) that will be:
1. Write the complete memory (ignoring Tcsm)
2. Read the complete memory in smaller junks honoring Tcsm

I would assume, that writing the complete memory will cause a complete refresh and that afterwards the self refresh operation will start running as before?

Best regards
Bernhard Wörndl-Aichriedler

[PradiptaB_11 · Accepted solution]

Hi

Yes, if you are operating below or about 85 C then  it should be fine to violate Tcsm as long as you ensure, that the complete memory is read/written within 64ms. Your understanding is correct here. 

If in your application if you fail to read/write the entire memory once every 64 ms then the memory will not be holding reliable data. So either you can decide to extensively read/write the memory or use the internal refresh circuitry by using the tCSM whichever is more suitable for your application. Please note that in option 1 you will consume more current. 

Thanks,

Pradipta.