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Hyper RAM Forum Discussions

GeFu_3059156
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Welcome! First question asked First reply posted

I am working on a HyperRAM controller in a MACHXO3 FPGA for this device.....

S27KS0642GABHI020

How is everyone handling the read cycle clock alignment? Variation over PVT is significant.

From the data sheet RWDS and DQout track each other tightly but they vary relative to the clock by a lot

1ns < tCKD < 5ns (clock to DQ valid)

0ns < tCKDI < 4.2ns (clock to DQ invalid)

My target clock is 125MHz (8ms)

At 125MHz the data valid window is....

3.0ns <  tDV < 3.2ns

but the window center varies a LOT.

2.5ns < tCENTER < 6.6ns (delay from the clock edge)

For this to track over PVT is to use RWDS (edge aligned with the data) as the clock but RWDS is not  free-running for a dynamic phase-lock.

A fixed delay from RWDS is possible but a known fixed clock period is required if guaranteed center alignment is desired.

What are your recommendations?

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ritwicksharma
Moderator
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Hi @GeFu_3059156,

 

We provide the Hyperbus controller IP. Please visit the link and fill out the form. Our internal team will review it, and after that, they will share the link to the IP.

 

Thanks,

Ritwick

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ritwicksharma
Moderator
Moderator
Moderator
250 sign-ins 100 replies posted 50 solutions authored

Hi @GeFu_3059156,

 

We provide the Hyperbus controller IP. Please visit the link and fill out the form. Our internal team will review it, and after that, they will share the link to the IP.

 

Thanks,

Ritwick

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