HyperRam readback data is always random

johnsonlee0805 · ‎Jun 04, 2021

Hi,

I am testing the S27KS0642GABHI020 on our board with Lattice crosslink-NX FPGA. I have 2 hyperbus controllers to use, one is the cypress hyperbus 2.0 controller and the other is a much simpler one from Lattice. I firstly tried the one from Lattice, I found no matter what I wrote into address 0 I always read back random data, even I didn't write. To avoid the wrong initial latency issue, I looked at the incoming data waveform from Lattice Radiant Reveal logic analyzer, they are always random data (mostly 8'h15). I also probed pins with scope to confirm data is coming from HyperRam. HyperRAM is running at 60MHz, but I also tried as low as 24MHz or higher at 120MHz, all similar results on reading.

What should I check? I also tried manual reset for Hyperram after power up.

Thanks,

Yuecheng

PradiptaB_11 · ‎Jun 04, 2021

Hi,

1) Can you provide us the schematics of the Hyper ram portion so that we can evaluate it once.

2) Can you kindly let us know more on the read failures. Is only address 0 is failing or any other address is failing as well. Also how many devices is showing this behavior.

3) Can you pass us the scope shots of read and write waveforms to the hyperram with only the control signals and data signals of the hyperram and remove other signals. This way we will be able to understand the issue more elaborately.

4) Are you able to read the Configurations registers of the device successfully or is it also giving error. Please pass on the values that you are reading from the CR0 and CR1 registers.

Thanks,

Pradipta.

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HyperRam readback data is always random

HyperRam readback data is always random

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