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JeanL
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Hello,

On our board we have one HyperRAM (S27KS064 1 DP B HB 02) and one HyperFlash (S26KS512S DP B HM 02).
These memories are connected to a FPGA through a shared bus (Y topology). FPGA implements one CYPRESS HyperBus controller that is connect to HyperFlash through first Chip Select and connected to HyperRAM connected second Chip Select. HyperBus memories at clocked by FPGA with a 100MHz clock.
At power-up, a controller inside FPGA initialize (in sequence) the HyperBus controller, HyperFlash and HyperRAM with following values:
• HyperBus controller
MTR0: 0x00110001
MTR1: 0x0011000F
MCR1: 0x807C0013
• HyperRAM CR0: 0xFFF5

During integration tests, we have some problem with the HyperRAM component.

First, we are not able to read the written value in CR0. Indeed, when we read the CR0 of HyperRAM we read always 0xFFFF or 0x5555.
When we change the written value of CR0 we can observe an impact on our tests. So we think that register has been correctly written, but a doubt persists. When the CR0 is not written at power-up, we read the default value (0x8F1F) described in the component datasheet but not on the first read access.


The second problem has been observed for high temperature (superior at 85°C). We have performed thermal tests of the HyperRAM but we observe than some data inside HyperRAM are corrupted. The number of corrupted data increase at each HyperRAM contents verification.
For information, this is the test procedure that we use:
• Write pseudo-random data in the HyperRAM (the all 8Mbytes of the memory is written)
• Read and verify the content of the memory
• Start again the Read and verify process

The test has been performed at a temperature of 95°C. Which correspond to a die temperature of 105°C for the FPGA and a temperature less than 105°C for the HyperRAM component. So we are in the operational range of the components.

To identify the problem source and to discard a refresh problem, we have perform a specific test which consist to
• At +25°C:
o Write pseudo-random pattern to memory
o Read&check pseudo-random pattern (ensure that there is no error)
• Without doing any HBRAM access:
o Increase temperature to +95°C
o Wait for 30 min
o Decrease temperature to +25°C
• Perform read&check test

During this test we have seen no error. So it’s not a refresh problem.

Moreover, to discard a timing problem, we have perform a test at 95°C without HyperRAM CR0 modification by adapting MTR1 and MCR1 values has follows for HyperBus Controller:
• MTR1: 0x00110001
• MCR1: 0x807D0013
CR0 reset value is 0x8F1F.
During this test, we have observed no error.


The both problem has been reproduced on the S27KS0641DPBHI020 (Industrial HyperRAM gen1) component at 85°C.

So for this moment, we cannot explain these two problems and through all performed tests we think that is not a timing problem.

Have you seen similar problems ?

 

Additionally, we have performed a test with HyperRAM gen2 component (7KS0642GAHI02).

With the same setup above and by replacing HyperRAM gen1 component by a HyperRAM gen2 component the problem identify on Configuration register 0 disappear. Indeed, with gen2 component we are able to write and read the CR0 register.

 

We have found an old datasheet of the component (001-97964 Rev. *E ) with an errata chapter.

The problem identify in this document is still valid ?

So, is there known issue on HyperRAM gen1 component ?

Is there an errata document ?


Thanks for your help
Jean

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2 Replies
Ritwick_S
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100 solutions authored 25 likes received 250 sign-ins

Hi @JeanL,

 

> Could you please let us know if you are compliant with the tVCS spec (VCC and VCCQ >= minimum and RESET# HIGH to first access)? (Reference- Section#7.5 Power-Up Initialization on pg#32 of the datasheet)

> Could you please share the power-on and power-down waveforms?

> Kindly share the schematic with us.

> Could you please share the first write and read waveforms just after the power-on?

> As the part used is industrial, the maximum operating temperature is 85 C. As you were operating at 95 C, you may observe some errors as you are not within the range.

> Also, when you replaced the Gen1 part with the Gen2 part, did you make any firmware updates?

> Did you also try writing/reading at high temperatures using Gen 2 part?



Thanks,
Ritwick

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JeanL
Level 1
Level 1
5 sign-ins First reply posted First question asked

Hi @Ritwick_S,

Before starting, thanks for your response.

> Could you please let us know if you are compliant with the tVCS spec (VCC and VCCQ >= minimum and RESET# HIGH to first access)? (Reference- Section#7.5 Power-Up Initialization on pg#32 of the datasheet)

Yes we are compliant with tVCS spec for Hyper and HyperFlash which has a greater tVCS than HyperRAM.

Bootsequence is controlled. Moreover, FPGA loading takes several hundred msecond after power supplies activation, and . So the first memory access is done after several msecond after power-up.

> Could you please share the power-on and power-down waveforms?

I can't share the power-up and power-down sequence. sorry. But I will try to share the maximum of informations.

Power supply of the memory is provided by the same power source  than FPGA I/Os connected to the memory.

Moreover, as said above, tVCS and tPD are covered by the board.

tRP and tRH and tRPH timings are covered by the FPGA through counters and reset manager.

> Kindly share the schematic with us.

I canno't share the schematic on a public forum. But RESET_N and CS pins have pullup resistor and DQ bus have serial resistor for signal integrity. Component has several decoupling capacitor (1uF and 100nF).

Moreover, a full signal integrity at corner case of all signals between FPGA and memories has been performed. 


> Could you please share the first write and read waveforms just after the power-on?

Due to board layout I cannot observe hyperbus signal. This the waveform from the simulation:

This is the first write access which is the CR0 configuration:

firstWrite.png

This is the first read access which is the CR0 checking (900ns after first write):

firstRead.png

> As the part used is industrial, the maximum operating temperature is 85 C. As you were operating at 95 C, you may observe some errors as you are not within the range.

We have perform testsn two HyperRAM components as explained in the first post:

  • S27KS0641DPBHB02: Industrial Plus (-40°C to + 105°C)
  • S27KS0641DPBHI020: Industrial (-40°C to + 85°C)

On the both part number the same problem as been identified. For the Industrial Plus component tests has been performed at an ambiant temperature of 95°C. For the Industrial component tests has been performed at 85°C (and below).


> Also, when you replaced the Gen1 part with the Gen2 part, did you make any firmware updates?

No Firmware updates has been performed. Indeed, during boot process, a controller inside FPGA configure the hyperbus controller and HyperBus memories (clock latency, ...) before use it. Configured value are compatible of gen1 and gen2 components (value has been given in the first post).

> Did you also try writing/reading at high temperatures using Gen 2 part?

Yes today. We replaced the S27KS0641DPBHB02 (gen1) by S27KS0642GABHV020 (gen2).

We the same FPGA (firmware) and board, problem disappear with gen2 component.

 

For information, next week i will be out of office. if I can I will answer

If not I will answer the week after.

 

Thanks for your help,

Jean

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