I have a question about the RWDS timing during the CA interval where simulation disagrees with the datasheet.
The simulation shows a HyperRAM write cycle where a refresh collision has occurred. RWDS changes in the middle of the CA interval signaling 2x latency. The datasheet only shows RWDS valid on CS# low.
If it is important to know when RWDS should be sampled to guarantee proper latency.
Infineon S27KS0642 1.8V 64Mb 200MHz
Clock is 125MHz. Initial latency set to 5. Variable latency enabled
Infineon memory model with the correct `define selected
Could you please clarify significance of the data packets present at the starting on Data line?
Could you please confirm RWDS in Test bench is not high at any instant?
Could you please provide the write timing parameters?
Line 1 is just a system clock for reference. 125MHz
1. The data at the leading edge of the diagram is finishing up a read cycle. You can see the final CK and CS# going high.
2. I can confirm that the memory and not the FPGA is driving RWDS in the timing diagram with the exception of the trailing edge of the diagram where the FPGA drives RWDS low (unmasked) as part of the write cycle.
3. Timing parameters. Please let me know what you are looking for.
CK# is 125MHz. Initial latency set to 5 in the control register. Variable latency enable in the control register. Simulation has verified reading and write to memory and control registers correctly with specified latencies.
In my experiments, I have added extra clock cycles to CS# high,width, and low timing to see if it affects when RWDS changes state.
These refresh collisions happen very infrequently. I find them by watching refresh signals internal to the HyperRAM model. My goal is to verify that the FPGA handles variable latency correctly.
Based on my experiments, RWDS low Z follows CS# falling but RWDS variable latency indication follows CK.
I can move the FPGA's RWDS sample point but the datasheet does not dimension this position .
Thanks for pointing out the issue. We reviewed the model and was able to replicate the issue. Please find the updated model with logic bug fixed. Please review and let me know if it solves the issue which you have seen in the earlier version of model.
Please find the attached model with this response.