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Hyper RAM

New Contributor

Hello everyone,

I asked the same question under HyperFlash board; however, this applies to the HyperRAM too since they follow the HyperBus timing specification all together.

Here is the link to the question: (Please review it, I'm not pasting it here to not to duplicate)

Question - HyperFlash Board 

For the CLK, DQ and RWDS timings, it seems like the datasheet values are valid only up to ~65 MHz, although it is specified up to 133 MHz. Delay values and the valid areas of given signals doesn't add up and there seems to be a mismatch.

Has anyone ever tried to design the interface themselves or debugged the interface above ~65 MHz (CLK)?  I'd like to see the DQs and RWDS signals (measured) above these clock frequencies.

Hopefully, @BushraH_91 , @TakahiroK_16 or other employees can answer. In the meantime, please feel free to comment if you're experienced on the topic. 

Thank you.

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