HyperRAM - HyperBus

[GoKo_4683011]

Hello,

We are using the STM32L4R5 (Nucleo-144, L4R5ZI-P) to implement HyperRAM memory (S27KL0642) under hyperbus protocol. There is a problem between OCTOSPI and serial communication. Sometimes, when the OCTOSPI is being activated the serial port doesn't work.

Any help will be appreciated. 

[PradiptaB_11]

Hi,

We will need more information to understand the issue better. 

1) Can you pass on your schematics for this application for the HyperRAM device.

2) Are you able to read the device ID. If not then the connections are not proper. 

3) If you are able to read device ID then do provide scope shots of read and write operations.

Thanks,

Pradipta.

[Stark38]

Hi,

Here is the schematic we followed for the HyperRAM device wich is provided in datasheet:

About the device ID, we can't read it but the memory drives RWDS. Maybe the timing specifications are wrong.

It seems that the motherboard keep waiting an answer from the device.

Thanks,

Stark

[PradiptaB_11]

Hi,

The connections or timing specifications may be faulty if you are unable to read the device ID. We will need more inputs from your side to debug this together. Can you share the timings used for this. 

If you are not comfortable on sharing the data on public forum (due to confidentiality) we can  move to a case support.

Thanks,

Pradipta.

[Stark38]

Hi,

I have an update: I can read the device ID. For the device S27KL0642, I read 0x0C81.

For the timing specifications, I used:

• Frequency = 60 MHz
• Trwr = 6
• Tacc = 6
• CS Bound = 15 (higher value also work)
• CS# = H = 1

But reading the device ID didn't relsove the memory reading operation.

I tried to write a specific data (0xAB) to an address:

Command sequence:Frame shape:Data sequence:

And when I try to read, this is what I have:

Command sequence:frame shape:Data sequence:

If I can access the device ID without issues, shouldn't I be able to access the memory ?

Thanks,

Stark

[PradiptaB_11]

Hi Stark,

1) Can you kindly provide the complete screen shots from the logic analyzer. In some snaps the labels are not visible and in very few of them we can see the time co-ordinate. It is difficult to infer much info from partial snaps.

2) Please provide a snap of all the timing parameters for the simulation. 

3) As now you are able to read the device ID we can rule out any error in the schematics. So mostly it is the timing settings which may be leading to these errors.

Thanks,

Pradipta.

[Stark38]

Hi Pradipta,

I'm sorry I don't have the logic analyser anymore. About the labels, the first is DQ[7..0], the second is CS, the third is CLK and the fourth is RWDS.

Maybe we can talk about the parameters I used:

• Frequency = 60 MHz
• Trwr = 6
• Tacc = 6
• CS Bound = 15 (higher value also work)
• CS# = H = 1

Do you think they are correct?

Kind regards,

Stark

[PradiptaB_11]

Hi 

On the parameters 

60 MHz is ok to use

Trwr = It should around 50-60 ns or higher

Tacc= It should around 50-60 ns or higher

Chip Select HIGH Between Transactions = >10 ns

can you kindly confirm all the parameters are as per above.

Thanks,

Pradipta

[GoKo_4683011]

Hello,

My colleague answered your questions.

Any help will be appreciated.