This isn't a HyperRAM question in particular, but this seems like the best place to post this. I am working on a Xilinx FPGA design that is interfacing with an STM32H microcontroller. We were hoping to operate in HyperBus mode (which the microcontroller supports), but with the FPGA as the slave. I know from this thread that Cypress did not supply a slave version of their IP core in 2019, but I was hoping that that might have changed by now: https://community.cypress.com/t5/Hyper-RAM/Using-an-FPGA-as-a-HyperBus-slave/m-p/136850#M84
It appears to me that the only way forward is to design a core by hand, but I was hoping to avoid that if possible.