Hyper RAM（S70KS1281DPBHI020）のSim Modelについて

[ToIk_1341346]

レジスタをRDする際にデーターシートではレイテンシなしと理解したのですが、

シミュレーションモデルではレイテンシがあるようです。

ここの仕様はどのようになっているのでしょうか？

[PradiptaB_11 · Accepted solution]

Hi,

Regarding the latency count by default it is six clock cycles for the part number you have mentioned. Please refer to page 21 of the datasheet and refer to initial latency row. You will also find more information on this on page 23 of the datasheet.

https://www.cypress.com/file/183506/download

Thanks,

Pradipta.

[ToIk_1341346]

Hi 

As you can show simulation data  which is the below. The wave form of simulation data is different from datasheet. In the data sheet, RD data is appear next to command address but in the simulation, it appear far from command address on DQ. 

 

[ToIk_1341346]

Hi 

As you can show simulation data  which is the below. The wave form of simulation data is different from datasheet. In the data sheet, RD data is appear next to command address but in the simulation, it appear far from command address on DQ. 

[PradiptaB_11]

Hi,

Please note that while you are reading a register or device ID or the memory space you will observe latency in each case, for the device. Only for the Write operation which is performed on register space you will not see any latency. The figure which you a referring to from the datasheet is for writing /loading   a register. For a read operation there will always be latency. So what you are observing in the simulation is in sync with the datasheet. If you will refer to our test bench for the model you will see that when a command for register write is given only then there is no latency and data follows out immediately. 

Thanks,

Pradipta.