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Hyper RAM

wdshep
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In studying the Hyper Ram Bus Specifications and the timing of the bus signals specifically the relationship between RWDS and the 8 Data bits, I am not sure how to reliably clock the read data into my Intel/Altera FPGA.  I occurs to me that what is needed is a 3 or 4 ns delay line or a 90 degree phase shift to delay the RWDS strobe until the data is stable.  

It is evident that this problem can be solved by the availability of Hyper Ram Controllers.  Is there any available information on how this is typically accomplished???

Thanks,

Bill

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PradiptaB_11
Moderator
Moderator 500 replies posted 250 solutions authored 250 replies posted
Moderator

Hi Bill,

You can refer to our Verilog model for Hyper ram device which also has an example implementation of the controller side. Kindly go through it once and you will get the required information.

https://www.cypress.com/documentation/models/verilog/verilog-model-hyperbus-interface

 

Regards,

Pradipta.

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PradiptaB_11
Moderator
Moderator 500 replies posted 250 solutions authored 250 replies posted
Moderator

Hi Bill,

You can refer to our Verilog model for Hyper ram device which also has an example implementation of the controller side. Kindly go through it once and you will get the required information.

https://www.cypress.com/documentation/models/verilog/verilog-model-hyperbus-interface

 

Regards,

Pradipta.

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