I was looking at the product page for the S80KS5122GABHA023. On the FAQ it states the following:
In Asynchronous SRAMs, the address pins (Ax) can be assigned in any bit order. For instance, pin A15 of CPU can be connected to A0 of SRAM, A10 of CPU to A1 of SRAM etc. Address assignment can be made as dictated by layout or other board-level constraints; there is no restriction from the internal SRAM-addressing standpoint, unless otherwise specified in the datasheet.
Likewise, data lines can be assigned in any order, within a specific byte. For instance, D0 of CPU can be connected to D4 of SRAM, D1 of CPU to D6 of SRAM etc. However, the data bit assignment should not cross byte boundaries if byte level accesses are made. For instance, a higher bit data of CPU connected to lower bit data line in SRAM could result in conflict when performing byte-specific (lower byte or higher byte) accesses. If such individual byte-level accesses are not made, routing can extend beyond byte boundaries also.
Does this actually apply to HyperRAM such as the S80KS5122, is the FAQ just some generic FAQ that gets placed on all the pages? Could anyone provide some info about how this could be implemented on the HyperRAM? Can I just connect any data line to any pin on the MCU? I'm still new to HyperRAM so I am confused about this.
