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Hyper Flash

didi_4175006
New Contributor

Hi

I have two questions:

(1) how to understand  "Row and Upper Column Address" .

(2)  give an address 0x03006000, how to get the "Row and Upper Column Address" and "Lower Column
Address".

Looking forward to your reply!

thanks

ding

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9 Replies
SudheeshK
Moderator
Moderator

Hello,

Please see the below table given in page 11 of the datasheets. It gives explanation about all of the command address bits.

SudheeshK_0-1617098268253.png

As you can see from this table, Lower column address is same as the lower address bits of the system word address. It consists of A2-A0 of the system word address. Row and Upper column address is equal to bits A3-Amax of the system word address. 

Example: Consider the device S26KS512S. It has 32 Mega words (64 Mega Bytes) and we need 25 address lines to address each memory location A0 - A24. In this case lower column address will be A0-A2 and row and upper column address will be A3 to A24. 

I hope this answers your query. Please let me know, if you need any clarifications.

Thanks and Regards,

Sudheesh 

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didi_4175006
New Contributor

Hi Sudheesh 

I already replied to you yesterday, as follows,Please help me check that.

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didi_4175006
New Contributor

Hi 

I have checked the "Erase Operation Command Sequence" in the manual, it gives the address 0x07000000; the binary is 0000 0111 0000 0000 0000 0000 0000 0000, I think [2:0] = 000b is the valid column address, and [31: 3] = 0x0e0_0000 is the “Row and Upper Column Address”, but the“Row and Upper Column Address” is not the same as indicated in the manual,The “Row and Upper Column Address” shown in the manual is 0x0e_0000.

s26ks512.png

 

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SudheeshK
Moderator
Moderator

Hello,

The sector address mentioned in the datasheet is 0x0700000 not 0x07000000.

SudheeshK_0-1617185119569.png

(Screenshot from page 16 of the datasheet)

So the binary representation will be as below.

‭0x0700000 : 0b0000 0111 0000 0000 0000 0000 0000‬

A2-A0 : 0b000

A24-A3 : 0b00 1110 0000 0000 0000 0000 = 0xe_0000

I hope this answers your query. Please let me know, if you need any clarifications.

Thanks and Regards,

Sudheesh

 

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didi_4175006
New Contributor

Sorry I didn't read it carefully, thank you for your reply!

thanks

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didi_4175006
New Contributor

Hi Sudheesh

I have another question, now we already know "Row and Upper Column Address" 0x0e_0000,

But how can I get the row address and Upper Column Address.

Need your help very much!

thanks

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SudheeshK
Moderator
Moderator

Hello,

Please see the definitions for page and column address of HyperFlash below.

  • Page: A Page is a 16-word (32-byte) length and aligned unit of device internal read or write access
  • Column address: The Column address selects the burst transaction starting word location within a Row. The Column address is split into an upper and lower portion. The upper portion selects an 8-word (16-byte) half-page and the lower portion selects the word within a half-page where a read or write transaction burst starts.

I hope this helps you to understand the HyperFlash address better. You can find more details about HyperBus Specification from our application note, https://www.cypress.com/file/213356/download.

Could you please clarify, why do you want to split row and column addresses in you application?

Thanks and Regards,

Sudheesh

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didi_4175006
New Contributor

HI 

Generally speaking, the hyperflash device has 32 bytes per page, and the hyperflash device is two-byte aligned, then 4 address lines can be used to express the 32-byte length;

But now the low 16 bytes occupy the 3-bit address line;

In my opinion  the high 16 bytes It also occupies a 3-bit address line, so
A2-A0 means low Column address, A5-A3 means Upper Column address; A31-A6 means row address, which is also a page address.
As mentioned before, given address 0x070_0000
low Column address :000
Upper Column address: 000
page address: 0111 0000 0000 0000 00 -> 0x1c000
Is my guess correct?

Looking forward to your reply!

thanks

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SudheeshK
Moderator
Moderator

Hello,

As I mentioned in one of my previous responses, 25 bit address (A24:0) is required to address each word inside S26KS512S. Out of this 25 address bits A2:A0 are lower address bits and the rest A24:A3 is same as the CA bits (CA37: CA16). Could you please clarify why do you want to split row address and upper column address? Also, could you please let us know more details about your application?

Thanks and Regards,

Sudheesh

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