- S26HS01GT datasheet mentions the recommended drive strength settings. Can you please confirm whether the setting is matching with your PCB trace impedance values?
- Can you tell us what is the command for which the waveform has been captured?
- Is the signal captured from the flash pins or from the microcontroller pins? If the signal is captured from microcontroller side, can you please try to capture from flash side?
- Is it possible for you to provide the clock signal coming from the microcontroller as well?
- Please go through the 'Decoupling Capacitors Recommendations' mentioned in this Application Note about HyperFlash™ and HyperRAM™ Layout Guide and make sure your design follows it.
- We also recommend performing IBIS model simulations. Could you please tell me whether you have registered for the Semper Early Access Program or not? If you have not yet registered, you can go and register here. Once you have registered, you will have complete access to all Semper related documentation and models. After successful registration, you can get the IBIS model for S26HS01GT from this link.
Thank you and Regards.
Thanks very much for replay.
We have sim, result is OK, drive strength setting is same as sim setting.
when read, the test point is SoC side, clk and DQ1 wave as below.
When write, the test point is flash side, clk an DQ2 wave as below.
CLK is 196MHz.Wave(zoom) as below.
SoC is CYT4DN(Cypress).
1) 如果把频率降低(如 80MHz 或 50MHz)，波形有无改善？还是有~1V的半波吗?
If the frequency is reduced (such as 80MHz or 50MHz), is the waveform improved? Is there still a half wave of ~ 1V?
Is the state of DQ floating when flash is not in operation? For the graph of write operation, when the differential clock does not jump (the master control has no operation on the flash), the flash will not work. Why is the DQ line pulled up at this time? In addition, in the process of writing, flash will not output but passively input the command address data to be written, but at this time, the main control signal is about 1V half wave, which is strange.
For the read operation waveform, there are many cases where DQ is still high when the differential clock does not jump. Will there be multiple masters accessing the same slave at the same time? This may result in the possibility of waveform superposition and half wave.
Flash // Launch Semper Flash mode.
Flash_EWR_Random // Flash Erase-Write-Read(verify) for random data
Flash_EWR_55 // Flash Erase-Write-Read(verify) for all AA data
Flash_EWR_AA // Flash Erase-Write-Read(verify) for all 55 data
Flash_Erase // Comming soon!!
Flash_Write // Comming soon!!
Flash_Read // Comming soon!!
- Were you able to get rid of the half wave in your application? Since the half wave is present in the write and read operation both, we suspect it may be occurring due to some issue in the layout.
- How many devices are showing this behavior? Are there any flash devices which are working fine?
- Did you try to replace this flash device with another flash and check whether the issue persists?