Hyper Flash Forum Discussions

Guten Tag zusammen. Könnten Sie mir bitte mitteilen, ob es sich bei dem S29GL256S11DHVV20 auf dem Bild um ein Original handelt (Marking)?

Wenn ja:

Wir haben diesen für einen Bestückungsauftrag beschafft. Auf dem Board des Kunden sind immer 2 Stück verbaut. Bei dem Funktionstest des Kunden wurde angezeigt, dass ein Speicher 512mb haben soll. Es handelt sich dabei jedoch um die 256mb Variante. Kann es sein, dass sich die beiden gepaart haben und deshalb auf 512mb kommen?

Vielen Dank im Voraus.

Mit freundlichem Gruß:

Ronny

The blank check on S29GL128S10FHIV20 does not work for me.

I issue the command:

(*flash_cfi_dev->write_native)((alt_u8*)flash_cfi_dev->dev.base_addr + addr + 0x555, 0x33);

and then repeatedly the command:

status = IORD_8DIRECT(flash_cfi_dev->dev.base_addr + addr, 0); // Read status register

waiting for bit 0x80 to drop, indicating that the erase check has started.

Then I wait for the erase check to finish.

If I use the command 

status = IORD_8DIRECT(flash_cfi_dev->dev.base_addr + addr, 0);

I always get 0x28. No matter how long I wait.

When I use the command sequence:

(*flash_cfi_dev->write_command)(flash_cfi_dev->dev.base_addr, 0x555, (alt_u8)0x70);
status = IORD_8DIRECT(flash_cfi_dev->dev.base_addr + addr, 0);

I always get 0x80.

I get the same above results whether the sector is erased or not.

Hello everyone,

I'm trying to design (schematic and layout) an interface between an application processor and a HyperFlash memory from Cypress. Therefore, I'm trying to understand the timing diagram for RWDS and DQs relative to the CLK line. Here is the timing diagram representing the valid and invalid areas of the given signals:

(Clock frequency is set to 166 MHz and the operating voltage is equal to 1.8V)

This is how the clock signal looks like:

I am trying to recreate the timing diagram using a third-party application, to design the interface to guarantee the minimum setup and hold timings etc. Here is how it looks like: (Measurement level is VccQ/2)

I have created 2 scenarios, based on the datasheet values and both seems to be incorrect.

The first is where the RWDS valid region (t_CKDS) tracks the CLK transition on both edges. That's how I understood at first, according to the datasheet. However, in this scenario, the valid area of the RWDS signal is nonexistent. Minimum time to the RWDS valid is specified as 1 ns, the maximum is 5.5 ns, relative to the CLK. Well, the positive and negative clock width is equal to 3 ns typical (let's ignore any jitter etc.). So, until the next transition of the CLK, there isn't enough time for the RWDS to be valid. Same is applied to the DQx lines in this example.

In the second scenario (since the first one failed), I drew the t_CKDS only on the rising/falling edge of the CLK/CLK# signal. That gives the RWDS a valid area of 1.5 ns. However, it should be minimum 2.46 ns, according to the xSPI specification as far as I am concerned. Also, this gives the DQx signal a valid area of 600 ps maximum. On the datasheet the data valid has a minimum value of 1.7 ns (t_DV).

Obviously, I am missing something here. I'll be glad if anyone experienced can be of any help and point that out. How to interpret this timing diagram with the given values?

Thank you 🙂 

Hi, 

I have a question about < write buffer program> of s26ks hyperflash.

I want to write  multiple word  using sequence like this "555->AA->2AA->55->SA->25->SA->WC->WBL->DATA->DATA->DATA", which use single  "WBL"  followed by  multiple words data. Maybe this is different with datasheet as picture below.

My experiment results are those: 

1) In RTL simulaton  using  s26ks hyperflash  Verilog model,  my write buffer program command( "555->AA->2AA->55->SA->25->SA->WC->WBL->DATA->DATA->DATA")  succeed.

2)When i run same code  in   real s26ks flash memory, it failed.

So, i want to ask if s26ks  can support  write buffer program like  "555->AA->2AA->55->SA->25->SA->WC->WBL->DATA->DATA->DATA" or not?

Thanks a lot.

where can i download the TXS02612RTWR and S25FS128 ,or the other flash device  schemetic symbol and pcb symbol;my eda tool is AD20,thanks

I am trying to communicate with hyperflash through microblaze connected with hyperbus IP. But neither read nor write operation is taking place. I have simulated it and observed Command address field out from HYperbus IP. There is difference between the Hyperflash datasheet mentioned waveform and the one observed by me during simulation. I have attached images of code, waveform from simulation and from the datasheet

Can someone please let me know what mistake is causing problem in communicating with the hyperflash?

Hi

I have two questions:

(1) how to understand  "Row and Upper Column Address" .

(2)  give an address 0x03006000, how to get the "Row and Upper Column Address" and "Lower Column
Address".

Looking forward to your reply!

thanks

ding

Hello,
Where can I download S25HL512TFANHI010 complete datasheet ? I was writing to Cypress directly and they suggested to ask datasheet inside same company forum (like, they can't send it directly but I need spend time asking this in forum instead of getting it directly) , that is a bit strange

https://eu.mouser.com/ProductDetail/Cypress-Semiconductor/S25HL512TFANHI010?qs=BJlw7L4Cy7%252B6M3sHZp0BRA%3D%3D

Anyone?

Thank you !

Hyperflash is not responding to any commands except status register read. I tried word programming , buffer programming, sector erase, Chip erase, DeviceID reading but none of this worked. Everytime status register value remains 0x80.

Can someone tell me what could be the issue.?