Hyper Flash Forum Discussions

The HyperRAM data sheet says :

The host system may also effectively increase the tCMS value by explicitly taking responsibility for performing all refresh and doing burst refresh reading of multiple sequential rows in order to catch up on distributed refreshes missed by longer transactions.

The core DRAM array requires periodic refresh of all bits in the array. This can be done by the host system by reading or writing a location in each row within a specified time limit. The read or write access copies a row of bits to an internal buffer. At the end of the access the bits in the
buffer are written back to the row in memory, thereby recharging (refreshing) the bits in the row of DRAM memory cells.

Array Rows = 8192    Array Refresh Interval = 64ms     tRFH  =  40ns

We want to use the user-refresh option, but the data & appnotes give no examples or guidelines on the most efficient way to do this.

It was expected to find a "refresh++" command in the register space that would increment ROW and perform refresh inside tRFH, but there is no sign of that.

Does that leave a dummy read, as in This can be done by the host system by reading or writing a location in each row within a specified time limit. as the only way to implement user refresh ?

Here, we need to increment A21 - A9 (CA34 - 22) on each read, to scan the Rows.

However, that looks like a lot of wasted clocks ( around 22?! & >> tRFH ) for what should be a very simple task.

There also looks to be no method to disable the Auto-refresh, which means the user-refresh has to manage wasted Auto-refresh time slots, further impacting refresh energy efficiency.

Can you give any links to user-refresh examples, and suggestions on how to do this in the least possible time ?

In data sheet you registering "The EXPOSED PAD should not be soldered on the PCB."

Why did you choose packing with EXPOSED PAD?

If I do not solder the EXPOSED PAD still will by a contact between the EXPOSED PAD on the chip to the EXPOSED PAD in my PCB

What should I do if I have already EXPOSED PAD in my PCB?

What should I do?
 

Hi,
I have read the HyperBus Memory Controller IP specification (HyperBus_Ctrl_IP_Spec_v2p40) and I have an important doubt.
In this document are mentioned AXI and AXI_LITE as interfaces for Control registers (Figure 2 and  Figure 5)

This is confusing. AXI-LITE is a much more reduced protocol than AXI with support to fewer features, for instance AXI-LITE does not have burst support.
In Table 9 read/write transactions for Control Register Acces Port have burst size different than 0.

Shall I suppose that the connection with the controls registers is AXI?

Thank you