Hyper Flash Forum Discussions
Hyperflash is not responding to any commands except status register read. I tried word programming , buffer programming, sector erase, Chip erase, DeviceID reading but none of this worked. Everytime status register value remains 0x80.
Can someone tell me what could be the issue.?
Infineon’s HyperRAM can be used as an expansion memory for high performance embedded systems because it offers the industry’s highest performance, smallest footprint and lowest pin count 12 pin HyperBus or 12 pin Octal xSPI interface to reduce design complexity and PCB cost. High performance embedded systems in a broad range of market segments require DRAM for scratchpad memory or image buffering or any other high performing end applications.
Designers and customers in these segments require a DRAM with
- A small package to reduce PCB area
- High read/write bandwidth to maximize system performance
- A low pin count interface, multiplexed bus with other peripheral devices such as NOR Flash to reduce the number of PCB layers, design complexities and the PCB cost
In this post we will cover as to why microcontrollers require expansion memory, what are the challenges that designers face when selecting the memory and finally how HyperRAM can help the designers to simplify their design with the Industry’s Highest Throughput and Lowest-Pin-Count Self-Refresh DRAM for Embedded Systems and hit the markets quicker. We will also discuss about our HyperFlash + HyperRAM solution that we offer in the industry and what are the target applications for our HyperRAM devices.
Why do microcontrollers require expansion memory?
Microcontrollers have little RAM available with them due to several reasons.
First, embedded SRAM takes up a lot of silicon die area. This means that increasing the amount of RAM directly increases the silicon area of the chip and hence the cost. Second is the issue of process compatibility. Different architectures require different manufacturing processes; hence it is not possible to send different parts of the same chip through different processes. Since the RAM arrays are optimized in different ways than rest of the chip, therefore it is more economical to design the memory architecture to match with the microcontroller, as a single silicon wafer manufactured on the same process to produce individual chips.
Semiconductor foundries which manufacture RAM chips have dedicated processes for optimizing RAM, which are not applicable as is for the microcontrollers or other logic circuits. Thus, producing RAM on a microcontroller die would mean trade-offs. Since larger RAM arrays have an increased surface area, faults are more likely to develop, simply due to the increased die area. This decreases the manufacturing yield, thus increases the manufacturing costs.
Due to the challenges associated with integrating a large RAM with MCU, the MCU architects prefer to design the MCU with a bare minimum RAM size on the chip as possible just to fulfil MCU core fast processing such as cache/registers. While, additional RAM needs are addressed by attaching expansion RAMs such as Async SRAM, HyperRAM, or DRAM.
Challenges faced by System Designers
High-performance embedded systems need at least 64Mb of expansion memory for process/data intensive applications. Microcontrollers often do not have enough integrated memory for high-resolution graphics or data-intensive firmware algorithms. Also, many high-performance embedded systems require a small PCB form-factor. A closest obvious option to support such a high-density expansion memory needs are legacy Single data rate (SDR) SDRAMS. SDRAMs are offered in packages as large as 261 mm² which occupies a large PCB area. The challenge is always to keep the solution form factor as small as possible because the board space is the key aspect in many applications and in that case a large package area is not acceptable.
High-performance embedded systems need high read/write bandwidth. Low read/write bandwidth diminishes system performance. Traditional DRAM interfaces provide a low read/write bandwidth in the range of 100 to 166 MB/sec. The performance of the entire solution can suffer if the external memory is slow.
Traditional SDRAM must use a separate bus from the NOR Flash memory bus because they are not compatible interfaces. Using a separate bus for DRAM increases pin count. Traditional double data rate (DDR) DRAM interfaces require up to 31 control, address, and data signals. Higher pin count requires additional PCB layers to route signals, increasing design complexity, and PCB cost thus increasing the challenges for designers.
The Infineon solution to all the design challenges is the HyperRAM memory. HyperRAM memories are offered in 64 Mb and above densities. HyperRAM memory comes in 24 ball-BGA package with a size of 48 mm². It is the smallest package size for expansion memories in the industry. HyperRAM offers a max data throughput of 400 Mbytes/sec. The HyperRAM memory can share the same bus with the HyperBus NOR flash memory as described in detail in later sections.
HyperRAM At a Glance
Infineon KL/KS HyperRAM 2.0 self-refresh DRAM is available in operating voltages of 3 V and 1.8 V for embedded systems.
- HyperBus and Octal xSPI Interfaces compliant with JEDEC xSPI standard (JESD251A)
- Access time: 35ns (max), Clock rate: 200 MHz
- Double Data rate (DDR) read/write bandwidth: 400MBps or 3200 Gbps
- Configurable burst modes (Linear, Wrapped length, Hybrid)
- Configurable Output Drive Strength
- Partial Memory Array Refresh feature to optimize battery performance
- Active Current: 30 mA (max) at 85 C for 3V part and 25 mA for 1.8V rated part
- Deep Power Down and Hybrid Sleep mode
- DPD current: 12 µA (max) for 3V and 10 µA for 1.8V rated parts
- Available in Industrial (-40°C to 85°C), Extended Industrial (-40°C to 105°C), Automotive Grade 3 (-40°C to 85°C) and Automotive Grade 2 (-40°C to 105°C) options
- Package: 24 ball BGA 6 x 8 mm
- Densities: 64 and 128 Mb
Additional information on HyperRAM products can be found at: https://www.cypress.com/products/hyperram-20-memory
The HyperRAM + HyperFlash Solution
As microcontroller applications get more complex, developers need more Flash program memory for the application firmware. This is especially true with Internet of Things (IoT) endpoints that are starting to perform relatively complex edge computing. However, sometimes applications can expand to the degree where an external program memory is required, at that point developers need to choose between parallel or serial Flash. NOR Flash memory was first introduced in the late 1980s with a parallel interface: one bus for data/command (x8-bit or x16-bit) and a separate address bus with address bit-width proportional to the Flash density (e.g. 22 address inputs for a 64 Mb Flash density).
The performance of this interface was enough to meet the requirements of end applications like consumer set-top boxes and ADSL routers. The high pin count of the interface (e.g. 46 pins for 64 Mb density considering all inputs and configuration pins) was also acceptable, given its large package size and the relatively low number of peripherals connected to them. Over time, users wanted to replace Parallel NOR Flash memory entirely with SPI NOR memory. This led to the development of higher density SPI NOR Flash devices that also offered much higher throughput by going from a single I/O to a dual I/O – and ultimately quad I/O – interface.
The industry reached its performance limits with QSPI NOR Flash. This had the minimum set-up and hold timing that could be handled by a memory controller with a maximum number of acceptable Flash components for code execution. But Infineon, working very closely with SoC designers to understand their system performance requirements, anticipated the need for higher performance NOR Flash. To meet this need, the company developed the innovative x8-bit Flash HyperBus interface and brought it to the market in 2014. The Infineon HyperBus Interface increases the SPI I/O width from x4-bit to x8-bit. HyperBus is a versatile interface that supports both a NOR Flash, called HyperFlash, and a RAM called HyperRAM. This meets the low pin-count requirements that SoCs need, given their advanced process geometry and small package size on which any additional pin has a cost impact. HyperBus uses an innovative architecture to increase the frequency up to 200 MHz DDR. Operating on a single HyperBus simplifies Designs and reduces pin count.
The HyperBus is a x8 DDR interface designed to support more than three-times faster read performance compared to conventional NOR Flash memory and use only 11/12 (with differential clock) control and data signals for read and write transactions. With HyperBus, a complete memory subsystem (NOR and RAM) can be supported by a single, low pin-count interface and memory controller. Requiring just 13 pins (12 pins of HyperBus interface plus an extra Chip Select [CS2]), this ‑flexible interface elegantly removes the burden of additional costly DRAM memory controllers with high pin-count interfaces.
The HyperRAM memory targets all the market segments be it the automotive segment or industrial segment or the consumer segment. Automotive Instrument clusters provide drivers a centralized and easily viewable location for displaying all critical automobile information. Today’s instrument clusters provide graphical gauge readouts on large, high resolution color displays. Infineon’s Quad SPI, HyperFlash™ and HyperRAM™ memory products provide performance and density scalability to match instrument cluster system requirements. An example for automotive instrument cluster is presented below.
In the Industrial segment: HMI panels, Machine Vision, Thermal Imaging, IR Surveillance Cameras, Medical Scanners, Endoscopes are all target applications to name a few. Similarly, for Consumer segment: Thermostats, Wearables, Communication – IoT Modules, Modems, Routers are all target applications for the HyperRAM. An example for the displays in Industrial and consumer HMI is presented below.
We also have an example of HyperRAM as a Video Frame Buffer in home and building automated systems which can be viewed using the below link.
References and Links
- HyperBus Specification
- HyperBus Ecosystem Support
- HyperBus JEDEC xSPI Standard Compliance
- Drivers and Software
- Hardware Development Tools
- Application Notes:
HyperRAM Refresh Interval Optimization (AN209853)Show Less
When erasing S26KL512S memory sector. The data becomes FF but part of next sector is 0.
When I erase the sector I wait for the flash to be ready (Status Register (Device Ready Bit))
and I check the erase status is Ok (Status Register (Sector Erase Status Bit)).
Do you have an idea ?
Best Regards,Show Less
在debug过程中，发现当RESETNeg为低时，flash model中的reseted信号会被拉低；当RESETNeg为高的时候，reseted还是低。但在model中，当reseted为高时，才会对ospi发过来的指令和地址进行采样，所以ospi发的指令和地址根本进不到flash model中。
このレイアウトガイド内(4.1 章)で、「50 オームのシングルエンド インピーダンスと100 オームの差動インピーダンス (定格値) を維持しながら、CK とCK#の
Do you know HyperBus Memory solution provides an optimum high-performance memory subsystem with 70% fewer pins and a 77% smaller footprint compared to existing SDRAM and Quad SPI solutions?
Do you know HyperBus Interface is fully compliant with the JEDEC xSPI standard?
Please refer the following content to know more about our HyperBus Memory solutions and let’s discuss about it in this forum post.
- Meeting New NOR Memory Design Requirements with Cypress’ HyperBusTM Interface and Synopsys DesignWare® IP Whitepaper: https://www.cypress.com/file/468291/download
- HyperBus Overview Video: https://www.cypress.com/video-library/Memory/hyperbus-overview/307571
- HyperBus Memory Products: https://www.cypress.com/products/hyperbus-memory
- Semper Flash: https://www.cypress.com/products/semper-nor-flash-memory