The HyperRAM data sheet says :
The host system may also effectively increase the tCMS value by explicitly taking responsibility for performing all refresh and doing burst refresh reading of multiple sequential rows in order to catch up on distributed refreshes missed by longer transactions.
The core DRAM array requires periodic refresh of all bits in the array. This can be done by the host system by reading or writing a location in each row within a specified time limit. The read or write access copies a row of bits to an internal buffer. At the end of the access the bits in the
buffer are written back to the row in memory, thereby recharging (refreshing) the bits in the row of DRAM memory cells.
Array Rows = 8192 Array Refresh Interval = 64ms tRFH = 40ns
We want to use the user-refresh option, but the data & appnotes give no examples or guidelines on the most efficient way to do this.
It was expected to find a "refresh++" command in the register space that would increment ROW and perform refresh inside tRFH, but there is no sign of that.
Does that leave a dummy read, as in This can be done by the host system by reading or writing a location in each row within a specified time limit. as the only way to implement user refresh ?
Here, we need to increment A21 - A9 (CA34 - 22) on each read, to scan the Rows.
However, that looks like a lot of wasted clocks ( around 22?! & >> tRFH ) for what should be a very simple task.
There also looks to be no method to disable the Auto-refresh, which means the user-refresh has to manage wasted Auto-refresh time slots, further impacting refresh energy efficiency.
Can you give any links to user-refresh examples, and suggestions on how to do this in the least possible time ?Show Less
Does anyone know if these memory chips will survive gamma irradiation as used in sterilization of some medical devices?
If they do what strength gamma irradiation can they survive and is there any data, specifications or test results to back this up?
Thanks in advance Tim PryceShow Less
I am working with the s27kl0641 hyperRam model to validate the HyperRam controller, which I developped.
I want to test the behaviour of the memory, when interacting with the memory in the BurstType Hybrid 128.
At first I set the Bits of the Configuration register to CR[2:0] = 000. This is done correctly as can be seen on the ConfigReg0.png picture in the attachement. After setting the configuration register, I start a new write transasction in the memory space with the burst type wrapped burst. the start address of the memory is 0x5. So the burst should wrap at the addres 0x3F (63). one address of the transaction corresponds to 16 bit of data, where in the memory, one address corresponds to 8 bit of data. So in the memory, the wrap should occur after address 127 was written. I think, this is implemented wrong because the wrap occures already at address 63.
I think, the mistake should be in the file s27kl0641.vhd somewhere at line 990.
Do you agree, that this is a mistake?
Thanks in advance
In data sheet you registering "The EXPOSED PAD should not be soldered on the PCB."
Why did you choose packing with EXPOSED PAD?
If I do not solder the EXPOSED PAD still will by a contact between the EXPOSED PAD on the chip to the EXPOSED PAD in my PCB
What should I do if I have already EXPOSED PAD in my PCB?
What should I do?