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Hyper Flash Forum Discussions

larswallden
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First reply posted First question asked Welcome!

Hi, we have some problems using the NXP iMXRT1062 with combined S71KS512SC0 Hyper Flash and RAM connected via FlexSPI A+B with separate CS lines for Flash and RAM.

We boot from the HyperFlash and have data stored in the RAM. We want to copy a large array of 3MB from the Flash to the RAM but that doesn't seem possible with this setup since the HyperFlash and HyperRam share the same FlexSPI interface.

Is it possible to use RWW functionality with the S71KS512SC0?

What are the restrictions for us to use the Flash and the RAM of the S71KS512SC0  simultaneously?

Best regards,

Lars Wallden

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1 Solution

Hello,

RWW are fundamentally not qualified on our dual dies since they may result in overheating, too much noise on the lines and high current consumptions which may damage the bonding and the package itself.

However, the current use case will not require RWW since the write operation will be made to the HyperRAM which does not have a busy time at all.

The main constraint is the shared IOs between the HyperFlash and HyperRAM which would mean that the internal SoC RAM should be used as an intermediate storage for the data before copying it over to the HyperRAM. So even if you can use 2x FlexSPI controllers, you can’t copy from HyperFlash to HyperRAM directly due to the shared IOs.

For additional questions please contact NXP  since this is about host controller configuration.

Thank you

Regards,

Bushra

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BushraH_91
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250 solutions authored First comment on blog 500 replies posted

Hello,

Thank you for contacting Cypress Technical Support, an Infineon Technologies Company. Is it possible to share the code?

Thank you

Regards,

Bushra

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Hello,

RWW are fundamentally not qualified on our dual dies since they may result in overheating, too much noise on the lines and high current consumptions which may damage the bonding and the package itself.

However, the current use case will not require RWW since the write operation will be made to the HyperRAM which does not have a busy time at all.

The main constraint is the shared IOs between the HyperFlash and HyperRAM which would mean that the internal SoC RAM should be used as an intermediate storage for the data before copying it over to the HyperRAM. So even if you can use 2x FlexSPI controllers, you can’t copy from HyperFlash to HyperRAM directly due to the shared IOs.

For additional questions please contact NXP  since this is about host controller configuration.

Thank you

Regards,

Bushra

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Hello,

Thank you for the informative answer on how this memory functions and how we should write our code for it.

Best regards,

Lars

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