cancel
Showing results for 
Search instead for 
Did you mean: 

Hyper Flash

Berkj
New Contributor

Hello everyone,

I'm trying to design (schematic and layout) an interface between an application processor and a HyperFlash memory from Cypress. Therefore, I'm trying to understand the timing diagram for RWDS and DQs relative to the CLK line. Here is the timing diagram representing the valid and invalid areas of the given signals:

(Clock frequency is set to 166 MHz and the operating voltage is equal to 1.8V)

Berkj_0-1632952668073.png

This is how the clock signal looks like:

Berkj_1-1632952862419.png

I am trying to recreate the timing diagram using a third-party application, to design the interface to guarantee the minimum setup and hold timings etc. Here is how it looks like: (Measurement level is VccQ/2)

Berkj_2-1632953870788.png

I have created 2 scenarios, based on the datasheet values and both seems to be incorrect.

The first is where the RWDS valid region (t_CKDS) tracks the CLK transition on both edges. That's how I understood at first, according to the datasheet. However, in this scenario, the valid area of the RWDS signal is nonexistent. Minimum time to the RWDS valid is specified as 1 ns, the maximum is 5.5 ns, relative to the CLK. Well, the positive and negative clock width is equal to 3 ns typical (let's ignore any jitter etc.). So, until the next transition of the CLK, there isn't enough time for the RWDS to be valid. Same is applied to the DQx lines in this example.

In the second scenario (since the first one failed), I drew the t_CKDS only on the rising/falling edge of the CLK/CLK# signal. That gives the RWDS a valid area of 1.5 ns. However, it should be minimum 2.46 ns, according to the xSPI specification as far as I am concerned. Also, this gives the DQx signal a valid area of 600 ps maximum. On the datasheet the data valid has a minimum value of 1.7 ns (t_DV).

Obviously, I am missing something here. I'll be glad if anyone experienced can be of any help and point that out. How to interpret this timing diagram with the given values?

Thank you 🙂 

 

 

 

 

0 Likes
2 Replies
Berkj
New Contributor

It seems like to match the datasheet timing (read operation, t_CKDS, t_CKD, t_CKDI, t_DV, t_DSS, t_DSH) values, the clock frequency must be around ~65 MHz maximum. However, the values are listed for 133 MHz operation.

Plus, the CK transition to DQ/RWDS valid time delays appear to be fixed over the whole frequency of operation range. Is it really fixed or is it a print mistake in the datasheet? Is there any errata for the HyperBus specification?

What is the reason for the timing mismatches here? Thank you.

 

Berkj_0-1633011830091.png

0 Likes
PradiptaB_11
Moderator
Moderator

Hi,

Let me attach some Verilog simulations of the HyperRam GEN2 device to show you the data valid window. The measurements are for 166 MHz. 

clock3.0ns.PNG

 

datavalidwindow.PNG

 

So, if you observe the clock is 166 MHz (1st image) and the data valid window is roughly 2.1 ns (2nd image) which do satisfy the datasheet value of min 1.7 ns. I suggest you to to try out the Verilog simulations at your end as well so that you can also verify this at your end and understand the Hyperbus interface operations and timings.  

Thanks,

Pradipta.

0 Likes