General

Version: **

Integration of Ethernet Reduced Gigabit Media Independent Interface (RGMII) into the 32-bit TriCore™ architecture of AURIX™ TC3x requires an additional clock signal input called “GREFCLK”, which is not part of the RGMII standard. This clock is necessary to provide a skew on the TX and RX interface signals. A clock-to-data skew is necessary because RGMII is a double-data-rate interface, where the clock must be skewed in relation to data and control signals. Special care must be taken at the startup of that Ethernet interface. See the corresponding errata sheet of your device and search for “GETH_TC.002” for more information. 

The RGMII standard describes the following signals for data transfers at 1000/100/10 Mbps.

• TXD[0..3], TXCTRL, TXCLK
• RXD[0..3], RXCTRL, RXCLK

GREFCLK is a 125-MHz clock input and must be provided by the connected Ethernet component or an external crystal oscillator. RGMII allows 100 Mbps and 10 Mbps line rates. For these speed classes, GREFCLK stays at 125 MHz while TX and RX clocks run at 25 MHz or 2.5 MHz.

 Summary

• GREFCLK must be provided on TC3x running an RGMII interface.
• Handle the Ethernet interface at startup.
• To downgrade speed from 1000 Mbps to 100/10 Mbps, the required GREFCLK frequency stays at 125 MHz input clock.

Version: *A

For each storage port, the theoretical data rate at which data will be transferred can be calculated as follows:
Data rate (MBps): SD_CLK frequency * data bus width/8

• SD_CLK frequency: Frequency of output clock (storage port)
• Data bus width: Storage port bus width

Table 1 shows the conditions required for maximum throughput.

Table 1    Requirements for maximum throughput

The standard Windows mass storage driver uses tiny bursts (64 KB) for mass storage data transfers, and the performance obtained is limited by various protocol overheads.

For the performance of EZ-USB™ FX3S with RAID 1 firmware, see section 8 of AN89661.

Version: **

A “Code Example” or “Expert Training” is a fully working project (for AURIX™ Development Studio (ADS)) that demonstrates how to configure and use one or more modules and features of AURIX™ microcontrollers.

An expert training is composed of two parts:

• Source code
• Tutorial

The source code of each code example is based on Infineon Low Level Drivers (iLLDs) and can be found at Infineon GitHub or directly imported within ADS using the dedicated import function:

File >> Import... >> Infineon >> "AURIX Development Studio Project", select "Infineon Code Examples Repository" and select the code example to be imported.

You can also click Import AURIX Project in the Quick Links view of ADS.

Each component of the code example is explained in the tutorial. The tutorial can be accessed from a dedicated Infineon webpage, or opened in ADS by pressing Ctrl key and clicking the link in the comment section of the Cpu0_Main.c file (see line 37 in Figure 1).

 Figure 1   Cpu0_Main.c file

Note:   This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC2xx series
• AURIX™ TC3xx series

Version: **

In the AURIX™ Development Studio (ADS), it is possible to replace the current version of files with an older one by browsing through the local history.

This feature is inherited by Eclipse™. Right-click on a file and select Replace With > Local History... as shown in the figure below to replace the content of the file.

 Use Compare With feature to compare older versions when it is not needed to replace the content of the file.

By accessing the Local History, a compare window appears from which the revision time can be selected. Double-click on the revision time, a compare viewer window of the two versions of the file is displayed. The changes can be replaced by clicking on the Replace button.

• AURIX™ TC2xx series
• AURIX™ TC3xx series

Version: **

AURIX™ Development Studio (ADS) inherits different Eclipse™ features, one of which is the Open Call Hierarchy. This helps you to find where a method is called or a variable is used inside all the open projects.

To access this feature, select the method or the variable and right-click on it, and select Open Call Hierarchy option as shown in the below figure.

Note:   You can also access it by pressing Ctrl + Alt + H keys.

Note:     This KBA applies to the AURIX™ Development Studio.

Version: **

Follow these steps to use a precompiled library in an AURIX™ Development Studio project:

1. Right-click on the project, select Properties -> AURIX™ Development Studio -> Build, and uncheck Auto-discover compiler include paths. It allows you to edit the include paths manually.

2. Click on Active Project Properties from the toolbar and select TASKING C/C++ Compiler -> Include Paths.

3. Add a new Include by clicking on the Add… button, select the folder containing the header file, and then click OK twice to return to the Project Properties.

4. Select TASKING Linker -> Libraries.
5. Select Add… -> Workspace and select the *.a file of the library.

6. Click OK twice, then Apply and Close Now you can call the library methods and functions from within your project.

Note:   This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC2xx series
• AURIX™ TC3xx series

Version: **

AURIX™ Development Studio (ADS) inherits different Eclipse features. Using the Rename feature from Refactor, you can rename variables, methods, or other items in code, and make sure that the element used in every instance is updated correctly.

Do the following to access the Rename feature:

1. Select the item that you want to rename and right-click it.
2. Click Refactor and select Rename….

Note:  You can also access it by pressing Alt + Shift + R keys

3. Enter the new name and press Enter to rename as shown in the following figures.

• AURIX™ TC2xx series
• AURIX™ TC3xx series

Version: **

1  Hardware modifications

Do the following hardware modifications to convert EZ-USB™ HX3PD as a 7-port Type-A DS and a Type-B US port hub as per CY6611 EVK Design:

1. PD regulator is no longer required as it is needed only when Type-C PD is enabled.
2. Connect an external Rd termination (5.1k) on one of the CC pins for each Type-C port and connect the corresponding set of superspeed lines from EZ-USB™ HX3PD to the US or DS connector. The other set of superspeed lines can be left floating.

1.1    Convert the HX3PD Type-C PD US port to a Type-B port

1. Add a potential divider circuit between VBUS_MON_P0 (pin D4) and US_TYPE_B_VBUS (VBUS from Type-B Upstream connector) as shown in Figure 2.
2. Based on VBUS from the Type-B connector (as shown in Figure 2), CCG4 will enable VBUS to turn ON the hub as shown in Figure 3. VBUS_C_CTRL_P0 (H4 pin) will output VBUS_US (VBUS signal to the HX3PD Hub controller) to enable the hub for normal operation.

1.2     Convert the HX3PD Type-C PD DS1 port to a Type-A port

1. Connect a potential divider circuit between VBUS_MON_P1 (B5 pin) and DS1_TYPE_A_VBUS (VBUS from Type-A downstream connector) as shown in Figure 5.
2. Connect VBUS_P_CTRL_P1 (pin D6) to the enable pin of the DS1 power switch as shown in Figure 4.
3. Connect VCONN_MON_P1 (pin C8) to the hub pin PWREN_P1 (pin J6) as shown in Figure 5 and Figure 6.
4. Connect OCP_DET_P1 (C6 pin) to the power switch’s overcurrent detection pin as shown in Figure 4. Make sure that it goes to OVCUR_P1 (pin K6) of the hub.

2     Firmware requirements

1. No firmware modifications are required.
2. Load the EZ-USB™ HX3PD Rev. A silicon with v1.3.0 and the EZ-USB™ HX3PD Rev. B silicon with v2.0.0.
3. Firmware for all the controllers of EZ-USB™ HX3PD (Hub, PD, DMC) should be valid.

Version: **

 1.     Hardware modifications

To enable the PD on DS2 instead of US port do the required hardware modifications from the CY6611 EVK Design. By default, Port-0 of the HX3PD PD controller is connected to the US port of EZ-USB™ HX3PD, and Port-1 is connected to DS1 of EZ-USB™ HX3PD. Port-0 of the EZ-USB™ HX3PD PD controller is connected to DS2 instead of US in this modification, and Port-1 is left unchanged.

1. Connect CC1_P0 and CC2_P0 to the DS2 Type-C connector as shown in Figure 1.

2. Connect PWREN_P2 to VCONN_MON_P0 as shown in Figure 3 and Figure 4 and pull-up to 3V3 as shown in Figure 2 (as handled in DS1).

3. Connect OCP_DET_P0 to the OVCUR_P2 pin, as shown in Figure 3 and Figure 4.

4. Connect VBUS_MON_P0 to VBUS of DS2 with RC circuit as shown in Figure 4 (as handled in DS1).
5. VBUS pin (upstream VBUS input) can be controlled by an external microcontroller GPIO or based on the VBUS detection from the upstream port.
6. Connect VBUS_P_CTRL_P0 and VBUS_DISCHARGE_P0 to the PD circuitry of DS2 (as handled in DS1).

7. Connect the first pair of upstream super-speed lines to the upstream port connector and the second pair of upstream super-speed lines is NC (No Connection), when DS2 is enabled for PD as shown in Figure 5.
8. Upstream port can be a Type-B port or a Type-C plug. If you want to use a Type-C receptacle, external CC detection is needed (by either a USB super-speed Mux or any other Microcontroller) and the corresponding super-speed lines from the Type-C receptacle should be connected to the first pair of upstream super-speed lines of EZ-USB™ HX3PD.

2 Firmware modifications

The latest HX3PD firmware (v2.0.0) is modified to support PD on DS2 of EZ-USB™ HX3PD instead of the upstream port and the firmware binaries are attached to this KBA. You can use the HX3PD configuration utility to change the DMC and PD controller configurations.

According to CY6611 EVK, VBUS_P_CTRL FET is set to Active High. To modify this configuration in firmware, contact Infineon support.

Version: **

The timeout value of the CPU0 WDT can be calculated using the following formula:
timeout = ((2^16 - STARTVALUE) * Divider) / f_SPB

Where:

• f_SPB is the frequency of the Serial Peripheral Bus
• STARTVALUE represents the fixed value 0xFFFC for calculating the timeout period and the user-programmable reload value REL (bitfield of register WDT0CON0) for calculating the normal period.
• Divider represents the user-programmable source clock division, which depending on the values of the IR0 and IR1 bitfields of the WDT0CON1 register, can get the following values:
• Definition of bitfields

The same formula applies to the other existing CPUs, replacing WDT0CON0 and WDT0CON1 registers, respectively, with WDTxCON0 and WDTxCON1, where x represents the number of the CPU.

 Note: This KBA applies to the following series of AURIX™ MCUs:

• AURIX™ TC2xx series
• AURIX™ TC3xx series