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Gate Driver ICs Forum Discussions

Lync
Level 1
First reply posted First question asked Welcome!
Level 1

Hello,

 

We are using 6 1EDI3031AS chips for a SiC inverter. We design the circuit as recommanded in datasheet and the inverter can work properly to driver a motor under low DC voltage with peak torque. However, when we increase the DC voltage up to 700 V, there will be occasionally gate monitoring fault blocking the test.  It will be more often if we increase the output current. We have tried to adjust the Ron resistor, it helps a little but doesn't fix the problem.

Then we switch to a IGBT inverter with the same gate driver board, we test under 400 V DC voltage, similar gate monitoring fault occurs when we try to increase the output power of the inverter.

Currently we are blocked by this issue and don't have clear direction to solve it, do you have any suggestion or experience on this? Thanks for your kind reply in advance.

Regards,

Lync

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G_Anshika
Moderator
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Moderator

Hello Huancheng,
Thank you for the response.

I agree with my colleague.
Also, the gate signal VGATE at pin CLAMP/GATE ensures that the signal VTOUT reaches the threshold value of VGATE properly. The gate monitoring fault occurs when the following condition is violated. Please double-check this.

Secondly, please share the gate voltage, collector current, and VCE voltage waveform with or without fault to analyze the behavior further. 

Regards,
Anshika

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G_Anshika
Moderator
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Moderator

Hello Lync,
Thank you for posting on Infineon Community.

Can you please share the schematic of the circuit that you have designed for a better understanding of the problem? 

Regards,
Anshika

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G_Anshika
Moderator
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Moderator

Hi,
I recommend you to please perform the two pulse test on the device with the different current and voltage levels settings and check if the fault occurs. Try doing the test multiple times.

Please do share the gate voltage, collector current, and VCE voltage waveform with us if you face any issues.
Let me know the result.

Regards,
Anshika

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Lync
Level 1
First reply posted First question asked Welcome!
Level 1

Hi Anshika,

 

Thanks very much for your feedback.

 

Please refer to the attachment for the schametics of gate driver we are using.

 

By the way, when we are doing double pulse test, it seems when the duty of PWM is close to 0 or 100%, it's easy to trigger gate monitoring fault. With IGBT it is even more easier to trigger a fault than SiC when the ducy is not so close to the limitation. From the gate pulse waveform, it looks like there is no enough time for the SiC switch to turn on and off in a very short period. 

Then we limit the duty between 3% to 97% in software, and try to avoid gate monitoring fault due to run into this region. However, we still face gate monitoring problem when we increase the speed and torque of the motor. Do you have any comment here?

 

Regards,

Huancheng

 

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DriverAE
Employee
First reply posted Welcome!
Employee

Hi Huancheng,

In "Output.PNG" I see that you added a 3.3Ohm + 1nF Filter on "CLAMP". I assume that this pin is connecting to the "GATE/CLAMP" pin of 1EDI3033AS.

I do advise against this because of the following:

  • Gate monitoring is looking at the voltage on GATE/CLAMP pin - adding this filter will interfere with the feature and delay the arrival of the GATE voltage to the driver and possibly trigger gate monitoring unexpectedly 
  • GATE/CLAMP is also an active miller clamp. The internal pull-down strength is ~0.3 Ohm. When you add a series resistor you basically "destroy" this low ohmic path

Regards,

Matthias

 

 

 

 

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G_Anshika
Moderator
Moderator 100 replies posted 50 solutions authored 100 sign-ins
Moderator

Hello Huancheng,
Thank you for the response.

I agree with my colleague.
Also, the gate signal VGATE at pin CLAMP/GATE ensures that the signal VTOUT reaches the threshold value of VGATE properly. The gate monitoring fault occurs when the following condition is violated. Please double-check this.

Secondly, please share the gate voltage, collector current, and VCE voltage waveform with or without fault to analyze the behavior further. 

Regards,
Anshika

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