Hey, 

I am trying to use the 2EDF7275F driver to drive two MOSFETs (IMW65R048M1H) for high-voltage AC switching as attached, 

for the 2EDF7275F, I use two sources : S1: 3.5 V for the VDDI and S2: 12 V for the VDDA,

the datasheet and application notes only report the half-bridge case where the switches are connected between a high-voltage source and ground, in my case the switches are connected between a high-voltage source and a load, I am wondering in this case where I should connect the ground of the S2 to make sure that the circuit is still isolated, 

Also, please advise on the attached design in general, 

Thanks 

When 2ED2181S06F is used to drive the high and low side MOSFET, the low side can be turned on and off normally, but the high side cannot be turned on. The test is conducted under the condition of Vdc=0V when the DC bus is not turned on. The test results are as follows: power supply Vcc=12v, Vb=11.55V, Vho=8.29V, Vs=8.6V. Please attach the schematic diagram and ask for help on the cause and how to solve this problem.

I would be thankful if you give me their explanations and any valuable resources where it is explained best regards

In the data sheet for the 1EDN7511B the Static output characteristics show a range of High level (sourcing) output
resistance  of 0.42R to 1.46R and Low level (sinking) output resistance of 0.18R to 0.64R.

My question is what circumstances affect this value?

Can I expect to see this range of resistances across multiple parts or is this more closely related to operating temperature?

Thanks

Hello.

I can't access Calculator_EiceDRIVER.

I think " You are not authorized to access this service" is the problem.

(See picture below)

If I need permission to use this service, please let me know what to do.

Thank you.

The sampling parameters are shown as below.

1、How to calculate the sampling error of the chip? Is the error obtained by using SPI consistent with ADCPWM to read sampling data? We use the sampling to detect the voltage of Udc via a series of high tolerance resistors.Could you please provide a calculation process from your side？

2、How to remove the gain error and offset error through calibration？Or can we calibrate out the offset and gain errors to reduce the sampling error？

3、What are the all six kinds of errors meaning?How could we do to reduce the sample error? 

Description
2ED020I06-FI is a high-voltage, high-speed power MOSFET and IGBT driver with interlocked high-side and low-side referenced outputs. The floating high-side driver can be powered directly or through a diode and capacitor. In addition to logic inputs for each drive, the 2ED020I06-FI is also equipped with a dedicated shutdown input. All logic inputs are 3.3 V and 5 V TTL compatible. The output drivers feature a high pulse current buffer stage designed for minimal driver cross-conduction. Propagation delay matched to simplify use in high frequency applications. Both drivers are designed to drive N-channel power MOSFETs or IGBTs up to 650V.
Feature
• 650V Coreless Transformer Isolated Driver IC
• Rail-to-rail output
•Protective function
• Floating high-side drive
• Dual Channel Undervoltage Lockout
• 3.3V and 5V TTL Compatible Inputs
Advantage
• Space saving package
• Fast and robust design
• Improved performance
• RoHS Compliant
Application
• Motor control and drive
• Solutions for solar systems
• Industrial welding
• Uninterruptible power supply (UPS)

Writing: Perceptive-ic(Solution provider)

Hai

     i am developing a 3.3Kw PFC unit, in that i am using the 2EDN8524F as a gate dreiver for to drive 2 mosfets( in parallel-IPP60R080P7 or IPW60R037P7) but in our testing surpricingly mosfets are safe but this driver IC is failing after 3hrs.

what will be the problem.

for your refference i am attaching the drive part. for this concept we have considered the app note 

Hello everyone, 

We are developing a motor controller with the part 6EDL7141 in 3 shunts configuration, with FOC control.

We use the current sense amplifiers of the 6EDL and the noise level is really bad - somewhere around 35mVpp. Combined with a gain of 12 and a 1mR shunt (which seems to be quite normal), that gives us a noise of 3A, which is not acceptable for our application. You will see the noise at the amplifier output in the picture attached (measurement is AC, with a noise floor <1mVpp, BW is 200MHz, passive single-ended probe).

All 3 amplifiers show the same noise shape - which seems slightly correlated after switching, probably due to switching noise being higher than the noise floor, but after that switching transient, the 3 amplifiers noise don't seem correlated. 

The noise level is linked to the gain of the amplifier (the more the gain, the higher the noise level), but it is not a strictly linear relation. We are pretty sure that the noise comes from within the chip because shorting the input of the amplifier doesn't change the behavior, nor does cutting the trace at the output. Noise is also present when not switching the MOS (but the amplifier output has to be activated, otherwise the output is clean). The frequencies of the buck and the charge pump don't seem to affect the noise. Because the noise is not correlated between the 3 amplifiers, we believe it is coming from the amplifier itself and not from an external excitation source.

We thought it was coming from our layout, so we tried measuring on the demo board, but we have the same noise on the demo board.

Placing a capacitor at the amplifier output makes it oscillate very cleanly. Placing a 330R resistor at the output to the ground is the only thing that seemed to have reduced the noise significantly (to about 20mVpp instead of 35mVpp with the aforementioned settings).

Additional info about our system: 48V (tried varying that), 6PWM mode, not using built-in hall functions, no faults are declared apart from a buck OCP on startup, we are in 3.3V logic (quite clean), using internal voltage reference of 1/2DVDD, we have tried many output filter options but without much impact. Battery or tabletop supply don't make a difference.

We tried doing an FFT on the noise but without much success. In our design the noise usually seems to go around 1.2MHz, which is also the frequency at which it oscillates when placing a 10nF to GND at the output. 

has anyone experienced this?
Is it a known problem of this chip?
Does anyone have hints or ideas for a workaround? (Or any info/idea at all)

Thank you for your help, 

Baptiste.