Gate Driver ICs Forum Discussions
hello,
I am using the 6EDL7141 with an STM32 microcontroller and have several questions which I don't believe are answered in the datasheet.
First I will explain the problems I am having:
1. When VBUS voltage input is above ~7V and EN_DRV is enabled, the DVDD output shuts off. At this point the 6EDL consumes ~40mA @ 12V
2. When VBUS voltage input is above ~7V and EN_DRV is disabled (low), the DVDD is ON and at 3.3V setpoint.
3. When VBUS voltage input is a bit lower than 7V and EN_DRV is enabled, DVDD is ON and at 3.3V setpoint.
4. The 6EDL will not reply to SPI commands.
I expect that there is some fault when EN_DRV is enabled? But why is this related to input voltage?
Questions:
1. Does SPI communication from 6EDL require that EN_DRV is on (high)?
2. Why might I be experiencing the above behavior. I have capacitance close to load and close to output of 3.3V DVDD
I have attached a schematic.
Thank you,
Alec
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Hello,
We are working on a project and we are controlling a valve.
We are using TLE7242-2G and we have noticed something.
Although we do not enable transient mode (in message 6), if we use 2KHZ PWM frequency, new setpoint is reached immediately after the last pwm period.
Bu if we use a lower frequency like 140Hz, it takes tens of periods to current to settle. Wyh should this happen?
What we clearly noticed is that the current waveform is changed from triangular to rectengular PWM (because of the decrease in frequency). Should this effect transient mode?
2KZ ImmediateSettle
140HZ Slow Settle
140Hz waveform
Thanks,
Sercan
Show LessHi,
SDO Disable Time starts at the 0.8VDD point on the CSN rising. How do I choose the end point? According to the figure, there is a line at 0.8VDD/0.2VDD. One thing is before the line the device has already released SDO and it's high impedance. The signal SDO may charge or discharge somehow making a slow rising/falling edge. In this situation, if you take 0.2VDD/0.8VDD as end point, the tdissdo will be far longer than the rating value. In fact, it makes no sense since the device already realesed the pin, the time of rising/falling has nothing to do with the device. For another thing, there may not be a rising/falling edge.So 0.2VDD/0.8VDD may not occur.
is there any CAD libraries OR IC Footprints available for PCB designing (2ED1324s12p dual bridge driver IC). I cannot find any.
Hello,
I'm using the following topology to provide a noise-immune driving signal path to the isolated gate driver IC 1EDB7275FXUMA1. Is there any potential problem with this scheme? Is there a better/standard method for this?
Note: All components are on a PCB.
Show LessHi 英飞凌
关于9180有一个疑问,我在做测试时,想注入故障确认诊断机制是否能触发,以下两条诊断策略没有找到很好的方法触发,请问英飞凌有推荐吗?或者如下两条无需测试验证,英飞凌可以保证?
1、Special Event - Latent Fault Warning
2、Internal Errors 2 - Charge Pump 1 Overload Error
Show LessHello
Is there, inside the component, any circuit prohibiting the simultaneous activation of the HO and LO outputs in the event of a SET inside the internal logic of the component or during a simultaneous activation of its HIN and LIN inputs?
Thanking you in advance for your help.
Best regards
Pierre
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