Gate Driver ICs Forum Discussions

The trigger singnal I used is  a typical TTL singnal (50us pulse width，50ohm output impedance, 5V) produced by a digital singnal generator.

I just directly connect the trigger singnal to both INA & INB.(in fact I only use channel A to drive a mosfet IMBF170R650M1. channel B is just for trigger feedback)

But when I used a probe to detect the singnal @ sma port, there was  another pulse (about 1ms

width) after about 200us .

 channel A output singnal and the mosfet behavior is agreed with the singnal above.

 I dont understand how a single pulse trigger singnal create a much longer pulse followed when connected  to the driver IC 2EDF7275K.

Where can I find the CAD files for KIT_1EDB_AUX_SIC and KIT_1EDB_AUX_GAN. Gerbers will do, source files would be great (Altium, Eagle, etc package). Thanks!

https://www.infineon.com/cms/en/product/evaluation-boards/kit_1edb_aux_sic/

https://www.infineon.com/cms/en/product/evaluation-boards/kit_1edb_aux_gan/

Can you tell me how to initialise the TLE92104 without the uIO stick.  I need to reset the GENSTAT register, change the VSOVTH bit in GENCTRL1 to 1 for 24V supply operation and I would like to disable he watchdog.

Thanks

Ging

Hello,

I made a half bridge test board similar to EVAL_1EDF_G1B_HB_GAN but with 1EDS5663H and IGT60R190D1SATMA1 parts, and added a trimpot in series with the recommended 18k resistor to set tneg, but it doesn't seem to work, I don't even get the theoretical minimum tneg of around 190ns. Could the drivers be the old version which needs a capacitor?

I also get some nasty ringing on the high side gate drive, which component value would you recommend to change?

Thanks,

Joel

I use 3 pieces of Eice driver 2ED020I12-F2 to drive a 3-phase inverter. This driver has a Fault output for each channel which is supposed to activate when a desaturation fault has occurred. If so it should also switch off the gate drive output. I have tried this in another inverter bridge and it works great.

But now on another board,  at least one of the 6 channels are outputting this fault flag. (Don't know which one or how many because the outputs are tied together.) But the bridge still runs the motor!! All the RDY outputs are high and toggling RST doesn't reset the Fault output.

There must be more reasons that can make this output activate than just desaturation.

What is it that the driver doesn't like?

What am I doing wrong?

Kind Regards /Bengt

Hello,

we have a design with the IR2103S gate driver. The driver has a supply voltage of 12V and two 3.3V 20 kHz PWM signals on HLIN and NLIN pins. Unfortunately, none of the ICs we tested output any signal for the MOSFETs. Sometimes it happens that MOSFET output voltage increases very slowly with time. What might be causing such strange behaviour? Is there a reference design/layout/BOM we can use?

Additionally, why is there a discrepancy in common wire between the datasheet and the simulation model?

Thank you so much in advance.

I'm trying to communicate with a TLE92104 eval kit. I have the uIO stick and it's fine with that.

I can't write to any of the registers because the device is in fail safe mode.  sending 0xE3 0x00 0x00 to clear the GENSTAT register which replies when I send 0xE2 with alternately 0x0C 0x01 and 0x00 0x01.. I'm not sure why the 0x0C is there and I can see that there is a charge pump undervoltage as it is not running.  What else do I need to do to initialise this device?  I think I have allowed enough time for the EN pin to be asserted and I have left sufficient time between CS asserts. (20uS)

Ging