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gingpeakin
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Can you tell me how to initialise the TLE92104 without the uIO stick.  I need to reset the GENSTAT register, change the VSOVTH bit in GENCTRL1 to 1 for 24V supply operation and I would like to disable he watchdog.

Thanks

Ging

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Vinay
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Hi @gingpeakin,

Good Day!

 

Sorry for the delay in response.

 

You can disable the watch dog by sending

 

SDI --> [C1] (GENCTRL1 address) [00 A7] (Data for GENCTRL1) in frame 1 (C1 00 A7) --> GENCTRL1 register (setting UNLOCK bit) and

SDI --> [C3] (GENCTRL2 address) [43 80] (Data for GENCTRL2) in frame 2 (C3 43 80) --> GENCTRL2 register (setting WDDIS bit)

and please change the watch dog time period to 200ms and follow this sequence before starting the board.

then it will disable the watch dog.

 

In the screen shot attached (GRAB_6.PNG), SDO is 00 00 01, you are facing Charge pump under voltage, please check the capacitance value connected across Vcp. Recommended capacitance Ccp is 470 nF.

 

Thank you!

 

Best Regards,
Vinay

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Vinay
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50 solutions authored 100 replies posted 250 sign-ins

Hi @gingpeakin,

Good Day!

Thanks for posting your question in Infineon community.

 

 GENSTAT register can be reset using SPI communication. Please refer to section 8 Serial Peripheral Interface - SPI  in the data sheet (TLE92104-232QX-DataSheet).

 

VSOVTH can either be chosen as 19V threshold or 29V threshold, please refer GENCTRL1 register.

Vinay_0-1669302177836.png

 

How to disable the watchdog?

The watchdog is one possible protection against unintentional motor activation or, in the case of system failures such as SPI bus issues or microcontroller malfunction, therefore it is recommended to keep it enabled. However, for convenience, the WD can be disabled during the development phase.

The following sequence disables the watchdog:

1. SPI Frame 1: Set the UNLOCK bit (GENCTRL1)

Note: While setting the UNLOCK bit, the WDTRIG bit must be inverted to avoid a wrong watchdog failure. The default value WDTRIG right after a power-on reset is 0.

2. SPI Frame 2: Set WDDIS (in GENCTRL2)

If an SPI frame is sent between SPI Frame 1 and SPI Frame 2, then the UNLOCK bit is cleared. Consequently, the WD stays enabled despite the SPI Frame 2.

This sequence requiring two consecutive SPI frames and involving two different registers, prevents an unintentional deactivation of the watchdog with one single SPI command (for example due to a flipped bit).

 

Please refer question 1.5 in FAQ document (https://www.infineon.com/dgdl/Infineon-Frequently-asked-questions-for-TLE9210x-FAQDocument-v01_30-EN...)

 

Thank you!

 

Best Regards,
Vinay
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Thanks Vinay

 

I can clear the GENSTAT register by sending 0xE3,0x00, 0x00 and I can see from the SPI SD0 line that it has cleared.  However I am unable to send anything to the control registers and of course I cannot invert the WDTRIG bit in GENCTRL1 so the watchdog times out.  I can see this happenning by polling the GENSTAT register where I can see the WDMON bits counting up until they reach 0xC0 and the the CPUV bit is set in fail safe mode and the WDMON bits are cleared and it stays that way.  Cleary the control registers are now locked  but why can I not write to the before the watchdog times out.  A simple 0xC1 0x00 0x27 to set the WDTRIG bit returns 0x00 0x00 0x26 indicating that nothing has been written.  I mentioned using the uIO stick in earlier posts so I can see that the eval board is working and my SPI monitoring is set up correctly.

I've attached a screen shot that shows (I think) that I have cleared the CPUV bit in the GENSTAT register - the top decode is SDI and the lower decode is the reply SDO.

 

Where am I going wrong?

Thanks

Ging

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Vinay
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50 solutions authored 100 replies posted 250 sign-ins

Hello @gingpeakin,

Good Day!

 

By sending 

SDI --> 0xC1, 0x00, 0xA7 in SPI frame 1 and

SDI --> 0xC3, 0x43, 0x80 in SPI frame 2 is resolving your issue?

 

Thank you!

 

Best Regards,
Vinay
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Hi Vinay

Yes it does. I had another issue with an arduino SPI library that was
generating glitches in the SS line that had to be resolved first but now
everything is working as I expect it to.

Thanks for your help

Ging

Andrew Peakin BSc(hons) MIET

Ging Peakin Special Cameras Ltd.

T 01903 202874
M 07568 384217
E gingpeakin@gmail.com
W gingpeakinspecialcameras.com
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Vinay
Moderator
Moderator
Moderator
50 solutions authored 100 replies posted 250 sign-ins

Hi @gingpeakin,

Good Day!

 

Sorry for the delay in response.

 

You can disable the watch dog by sending

 

SDI --> [C1] (GENCTRL1 address) [00 A7] (Data for GENCTRL1) in frame 1 (C1 00 A7) --> GENCTRL1 register (setting UNLOCK bit) and

SDI --> [C3] (GENCTRL2 address) [43 80] (Data for GENCTRL2) in frame 2 (C3 43 80) --> GENCTRL2 register (setting WDDIS bit)

and please change the watch dog time period to 200ms and follow this sequence before starting the board.

then it will disable the watch dog.

 

In the screen shot attached (GRAB_6.PNG), SDO is 00 00 01, you are facing Charge pump under voltage, please check the capacitance value connected across Vcp. Recommended capacitance Ccp is 470 nF.

 

Thank you!

 

Best Regards,
Vinay
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