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Gate Driver ICs Forum Discussions

User21797
Level 2
10 questions asked 10 sign-ins 5 likes given
Level 2

Hi there,

As topic, I am confused with this 'latent fault warning' feature in TLE9180. More specifically what is the condition for lfw bit being setted in register Ser (addr 0x42)? I can't find any information in the datasheet or on MyISP website.

Snipaste_2022-07-15_14-54-20.png

Thanks for reading, any reply is appreciated.

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1 Solution
Jingwei
Moderator
Moderator 100 sign-ins 50 replies posted 25 solutions authored
Moderator

Hi,

thanks for using Infineon Community. For this Information, please contact the local Infineon Office or local FAE.

Best regards,

Steven

View solution in original post

1 Reply
Jingwei
Moderator
Moderator 100 sign-ins 50 replies posted 25 solutions authored
Moderator

Hi,

thanks for using Infineon Community. For this Information, please contact the local Infineon Office or local FAE.

Best regards,

Steven