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Gate Driver ICs Forum Discussions

User21519
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Level 1

Hello, I'm using TLE7242 and I want to use it to detect the load disconnection fault.

SPI #9 Diagnostic Read is for diagnose. The response message consists of these bits according to the manual:

01.jpg

02.jpg

I want to make sure my understanding of some concepts in the manual is correct. My understanding of Table 2 is:

"Open Load" means load disconnection.
"Gate" is the MOSFET pin controlled by OUTx.
"Gate is ON" means the MOSFET gate pin is active, and the source and drain pin is connected.

If Gate is ON for a long enough time, the on-state test can be done, the SB-TST bit in SPI #9 response will be 1.

If Gate is OFF for a long enough time, the off-state test can be done, the OFF-TST bit in SPI #9 response will be 1.

 

I've test these cases for a certain channel:
Output 0mA, connected, the diagnostic read result is stable:

01.png

Output 0mA, disconnected, the diagnostic read result is stable:

02.png

Output 200mA, connected, the diagnostic read result is stable:

01.png

Output 200mA, disconnected, the diagnostic read result changes for 3 times (from connected) and then become stable:

03.png

Output 830mA, connected, the diagnostic read result is stable:

04.png
Output 830mA, disconnected, the result is unstable. Following is the diagnostic read result from the moment of disconnection. The result keeps on changing.

03.png

I don't know how to detect the load disconnection in the program. It seems at low current,

 

disconnect=((OFF_TST==1) && (OL_OFF==1));

 

works fine. But the expression doesn't work at high current.

I've measured the OUTx behavior. The period is 600us. When output 830mA and the load is connected, the duty cycle is about 20%. (OUTx is high for 100us and low for 500us.) I think the off-state duration is long enough for a test,  OFF_TST should not be 0 when output 830mA and load is disconnected.

Am I using TLE7242 correctly? How can I detect the load disconnection when output current is high?

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1 Solution
AZIZ_HASSAN
Moderator
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Moderator

Hi,

As per your explanation, i feel the main problem is due set point. I feel that in your code, somewhere the timing signal is not operating properly.

Please check the loops in your code and try to see the executions each command when you do the test.

Since, the PWM pattern (low or high) looks fine, the MCU can give false error only when code command gets executed wrongly or when unwanted multiple commands activates.at a time. I insist please check your code commands especially where you are using for loops. Another idea which you can use is, disable the fault command from code side and see it is running fine or even  while running you are facing some issue.

 

BR,

AZIZ HASSAN

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5 Replies
AZIZ_HASSAN
Moderator
Moderator 100 sign-ins 50 solutions authored 10 likes received
Moderator

Hi,

Thank you for posting your query on Infineon community.

We understand that you are facing a issue of unstable result when current is high during off state.

First, I would like to inform  you that  your understanding about table 2 is correct.

Since, you are facing this issue, I request you to do the following diagnosis.

From hardware side-

1) Check your PCB layout and path inductance especially source and drain leakage inductance.

2) Check the supply voltage (V5D) fluctuations (if any )during off time.

3) If supply voltage is fluctuating then the V_signal will not be constant ( this may happen due to high leakage inductance and can be predominant at high currents) and your RESET_B pin can also change its state resulting in unstable output .

4) Check fault pin status whether its actually changing its state continuously at high current.

 

From software side-

1) Repeat the experiment at high current and high duty ratio and check whether you are facing same issue. If not then then there may be a issue of tested timer and fault timing signal error/mismatch.

2) Check code for any infinite loop when frequency mismatch occurs (as explained in point 1).

AZIZ_HASSAN_0-1640948297816.png

 

AZIZ_HASSAN_1-1640948331879.png

Please check you code and output as per the timing diagram given and the logic given for OFF- T bit ( when when the tested timer expires). It may happen that the fault timer and test timer may be out of specifications and it can result in random output.

In addition to it, if I am not wrong I can see that sometimes you get a short to battery error as well at the time of load disconnection fault  check during off period.

So, please check your set point (i.e. channel is turned off or not).

 

BR,

AZIZ HASSAN

 

 

AZIZ_HASSAN
Moderator
Moderator 100 sign-ins 50 solutions authored 10 likes received
Moderator

Hi,

I hope the unstable result shared by you during connected and disconnected state are for same single channel out of 4 independent channel of IC.

BR,

AZIZ HASSAN

 

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User21519
Level 1
First reply posted First question asked First like given
Level 1

Thanks for the reply. Here's the result I got.

V5D and V_signal are 5V all the time.
ENABLE, RESET, FAULT pins are high all the time.

Output 1000mA, OUTx period=600us, on duration=120us, on/all=20%.
Output 200mA, OUTx period=600us, on duration=24us, on/all=4%.

CLK is 26.667MHz, PWM divider is set to 500. The period is correct as Fpwm=Fclk/32/Divider=26.667e6/32/500=1666.6875Hz. PWMperiod=1/1666.6875=600e-6s=600us.

(Actually the CLK signal is not clear. But the period of OUTx is correct. Perhaps it's the problem of my oscillscope)

If it helps, kp=256, ki=10. I've tested with other values of PWM divider, kp and ki, but the current and diagnose seems not become better.

The MCU read diagnostic result every 3ms. In the original post, MCU would set setpoint to 0mA if (OFF_TSTx && OL_OFFx) keeps true for 100ms (means a stably detected disconnection). The occasional SB may come from that. Cancel the 100ms delay doesn't solve the wrong disconnection error

If I don't change setpoint to 0mA, the OUTx stays high when disconnected.

I don't understand the frequency mismatch part of your reply. Could you explain in detail? Thanks very much😜

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AZIZ_HASSAN
Moderator
Moderator 100 sign-ins 50 solutions authored 10 likes received
Moderator

Hi,

Frequency mismatch  means the fault time and tested time are not as per the specifications given in application note.

Please check you code and output as per the timing diagram given and the logic given for OFF- T bit ( when when the tested timer expires). It may happen that the fault timer and test timer may be out of specifications and it can result in random output.

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AZIZ_HASSAN
Moderator
Moderator 100 sign-ins 50 solutions authored 10 likes received
Moderator

Hi,

As per your explanation, i feel the main problem is due set point. I feel that in your code, somewhere the timing signal is not operating properly.

Please check the loops in your code and try to see the executions each command when you do the test.

Since, the PWM pattern (low or high) looks fine, the MCU can give false error only when code command gets executed wrongly or when unwanted multiple commands activates.at a time. I insist please check your code commands especially where you are using for loops. Another idea which you can use is, disable the fault command from code side and see it is running fine or even  while running you are facing some issue.

 

BR,

AZIZ HASSAN

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