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p_izard
Level 1
Level 1
5 replies posted 5 sign-ins First reply posted

Hello

Is there, inside the component, any circuit prohibiting the simultaneous activation of the HO and LO outputs in the event of a SET inside the internal logic of the component or during a simultaneous activation of its HIN and LIN inputs?

Thanking you in advance for your help.

Best regards

Pierre

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1 Solution
Meghana
Moderator
Moderator
Moderator
50 likes received 100 solutions authored 10 likes given

Hello @p_izard , 

RIC7113A does not have an internal shoot-through protection feature, which can shut down or prevent both HO & LO going high. However, the user can achieve this function by use of basic logic gates external to the driver on the input side as shown below. 

Option 1: Using NAND gate to control SD pin based on HIN and LIN input states. When both HIN & LIN goes high, SD pin is pulled low. Hence output stages will be shut down. 

Meghana_1-1691427337594.png

Meghana_2-1691427459063.png

 

Option 2: Use of NOT gate to build an interlock between HIN & LIN. However, user will have to add additional delay circuit in order to configure the deadtime between the two outputs. 

Meghana_3-1691427885719.png

Option 2 will require higher components to configure the interlock function which will consume more layout space and also add to the system cost, but it will allow you to control both the switches with single PWM control signal. But if its possible to have two separate PWM control signal for both the switches, then Option 1 is a simpler option. 

Hope this helps.

 

Regards

Meghana

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3 Replies
Meghana
Moderator
Moderator
Moderator
50 likes received 100 solutions authored 10 likes given

Hello @p_izard , 

RIC7113A does not have an internal shoot-through protection feature, which can shut down or prevent both HO & LO going high. However, the user can achieve this function by use of basic logic gates external to the driver on the input side as shown below. 

Option 1: Using NAND gate to control SD pin based on HIN and LIN input states. When both HIN & LIN goes high, SD pin is pulled low. Hence output stages will be shut down. 

Meghana_1-1691427337594.png

Meghana_2-1691427459063.png

 

Option 2: Use of NOT gate to build an interlock between HIN & LIN. However, user will have to add additional delay circuit in order to configure the deadtime between the two outputs. 

Meghana_3-1691427885719.png

Option 2 will require higher components to configure the interlock function which will consume more layout space and also add to the system cost, but it will allow you to control both the switches with single PWM control signal. But if its possible to have two separate PWM control signal for both the switches, then Option 1 is a simpler option. 

Hope this helps.

 

Regards

Meghana

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p_izard
Level 1
Level 1
5 replies posted 5 sign-ins First reply posted

Hi,

Thank you very much Meghana.

But SD pin is active high no? and rather than a NAND gate, we should use an AND GATE no?

Best Regards

Pierre

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Meghana
Moderator
Moderator
Moderator
50 likes received 100 solutions authored 10 likes given

Hello @p_izard , 

A high to low transition on SD pin will disable the outputs. This can be confirmed from the waveform definition provided in the datasheet (attached snapshot of the same below).

Meghana_0-1692169637094.png

Hence based on above logic, a NAND gate would serve the purpose we require.

Regards

Meghana

 

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