Hello Archit,
I understand that by "adverse effect" you are mostly referring to noise issues.
Issues may arise if the electric field of the main power loop (up to 300A) couples through the gate driver.
This can be avoided with a proper PCB layout.
For this, the electric fields created by the traces need to be contained.
This is achieved by always having the return trace of a power or data line immediately adjacent to it.
The layer stacking needs to contain these fields, such as:
The first example shows that the fields are contained, so the effect of the 6th layer on the 1st layer is minimal (as long as the patterns of layer 5 and 6 mirror themselves).
The second example shows that the reach of the electric field reaches to the 1st layer, so there will be adverse effects.
When I mention that the pairing layers (such as 1st and 2nd) should be mirrored, this only refers to the signals and their return line only.
Such as the 6th and 5th lines, in which the 5th layer should be like below or take even more space to contain the fields created by layer 6:
If you can close the loop correctly, the fields will be contained.
If the fields are contained, the fluctuations on the power rail will not reach the signal lines of the GD.
Therefore the GD fill suffer minimal adverse effects.
One last thing to note is that the gate signal has to go from one side of the PCB to the other.
This will increase the the gate loop compared to having the GD and MOSFET on the same side.
To minimize the loop, you could introduce a pairing via for the return current, parallel to the GD signal via.
Conclusion:
If proper PCB layout is adopted, the DG will have minimal adverse effects.
Best regards,
Pablo
Hello Archit,
I understand that by "adverse effect" you are mostly referring to noise issues.
Issues may arise if the electric field of the main power loop (up to 300A) couples through the gate driver.
This can be avoided with a proper PCB layout.
For this, the electric fields created by the traces need to be contained.
This is achieved by always having the return trace of a power or data line immediately adjacent to it.
The layer stacking needs to contain these fields, such as:
The first example shows that the fields are contained, so the effect of the 6th layer on the 1st layer is minimal (as long as the patterns of layer 5 and 6 mirror themselves).
The second example shows that the reach of the electric field reaches to the 1st layer, so there will be adverse effects.
When I mention that the pairing layers (such as 1st and 2nd) should be mirrored, this only refers to the signals and their return line only.
Such as the 6th and 5th lines, in which the 5th layer should be like below or take even more space to contain the fields created by layer 6:
If you can close the loop correctly, the fields will be contained.
If the fields are contained, the fluctuations on the power rail will not reach the signal lines of the GD.
Therefore the GD fill suffer minimal adverse effects.
One last thing to note is that the gate signal has to go from one side of the PCB to the other.
This will increase the the gate loop compared to having the GD and MOSFET on the same side.
To minimize the loop, you could introduce a pairing via for the return current, parallel to the GD signal via.
Conclusion:
If proper PCB layout is adopted, the DG will have minimal adverse effects.
Best regards,
Pablo
