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Gate Driver ICs Forum Discussions

sujoy
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I am designing a BLDC motor controller and facing some issues with using an IRS2007 along with IRFB3607.
4100.attach

For one phase, the high side and low side give clean wave forms as long as V_Pow is disconnected. Rise time - 300ns; Fall time-100 ns; On time - 312us; Period- 416us;

Once V_pow is connected, the input signal to the low side of the mosfet driver leaks to the high side and drives the gate of the high side mosfet. The gate of the low side mosfet is off.

This creates a high to high short over 2 phases of the motor and the motor immediately stops. This happened first time after running for about 1 min. Ever since, the motor does not run when powered by 3 phases.

The motor is a 48V 900W motor driven at 12V, no load (1A).

If driven by the two other phases, the motor runs.

------------------------End of current issue-----------------------------

Background:--------------------------

I have tried this configuration multiple times, at first I used a complimentary BJT (PNP_NPN) duo to increase the current pumped to the gate of the MOSFET

4101.attach

In this case the driver would work properly when V_POW was not connected but fail after V_POW was connected to 12 Volts.

Each time, with 3 phases and V_pow disconnected, the gate pulses would be in order. Once V_pow was connected, one phase would randomly fail before 1 cycle was completed.

After that the remaining 2 phases would happily power the motor till the failed Mosfet driver was replaced and then again within 1 cycle 1 phase would randomly fail.

In the above config, on mosfet driver failure, both HO and LO pins would be shorted with pins of V_Boost & V_in respectively. I presumed it was an internal MOSFET failure due to over current.

As of now I have destroyed 17 drivers trying to figure out what happened. Don't know what I am doing wrong, The power mosfets mosfets don't seem to fail. Max current through the power circuit is hardly 1 -2 amps.

Board Top
3987.attach

Board Bottom
3988.attach

I'll add scope pics in 1-2 hours.
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1 Solution
Emanuel
Employee
10 solutions authored 5 solutions authored First solution authored
Employee
Hi Sujoy,

glad we could help, even indirectly :). Somehow we overlooked the missing decoupling caps. But yes, ideally they should be as close as possible to the switches and the switching path kept as low inductive as possible.
You should also look into decoupling VCC and the bootstrap cap. The later is quite far away from the pins so the added inductance is not that good.
Do you know how large the spikes were?
I do not think that the the spikes would of coupled and damaged the driver (they should of been really high).
Did you by any chance also measured the middle point (VS) in reference to COM? did it went negative? how negative?
Most likely the Vs point went negative (in reference to COM) due to the very high inductance in the supply/switching path and this damaged the driver IC. This is an inherent problem of level-shift gate drivers, especially the "Junction Isolated" (Bulk CMOS) gate drivers, and while our technology is one of the most robust on the market, for this product we can generally allow COM - 8 V on the VS pin.
I think decoupling the 3 phases actually solved this negative spikes.
Please let me know if this problem reapers 🙂
Good luck with your project.
Best regards,
Emanuel

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15 Replies
Emanuel
Employee
10 solutions authored 5 solutions authored First solution authored
Employee
HI sujoy,

It this problem always on the same phase? or is it happening on all phases?
could you please post some scope pictures of your problem?
For the first circuit, could you please post a picture of the input PWM signals (both high and low) and HO LO?
For the second picture it would help to see the input PWMs and the gate signals for the high and low switch.

Best regards,
Emanuel
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sujoy
Level 2
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Level 2
Emanuel wrote:
HI sujoy,

It this problem always on the same phase? or is it happening on all phases?
could you please post some scope pictures of your problem?
For the first circuit, could you please post a picture of the input PWM signals (both high and low) and HO LO?
For the second picture it would help to see the input PWMs and the gate signals for the high and low switch.

Best regards,
Emanuel


I have updated the question and corrected the images to make the issue more clear. Let me know if it is okay.
Either ways I'll be uploading the scope images once I reach my desk in a few hours.
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Emanuel
Employee
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Employee
thank you for the clarification.
One thing which might create some problems in the PCB is decoupling of the gate driver. for the input you have no decoupling capacitors, while for the bootstrap capacitor, it is placed quite far away from the driver IC.

for both problems: It will also help to see the waveforms with the DC-link connected (V_POW) and without. In case the current is too high, disconnecting the load is also acceptable.

By looking at your schematic, I want to make sure that you are referencing the control signals to the GND of the gate driver. so both HIN and LIN are referenced to the COM pin and not to each-other. From your schematic, it seems that HIN-LIN are driven as diferential pairs and not referenced to GND.

Please measure:

HIN-COM
LIN-COM
LO-COM
HO-COM

Then also measure:
VIN-COM
HIN-COM
VB-COM
HO-COM

with and without V_POW (please also mention V_POW used). The measurements should be done on the gate driver pins.

For the second circuit (with boosters):
Please also measure:
LIN-COM
HIN-COM
Gate_RHIGH5-COM
GATE_RLOW4-COM

and mention the V_POW voltage

please make sure not to exceed your scope ratings when performing the measurements.
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sujoy
Level 2
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Level 2
Ignore the 2nd configuration for now. I just mentioned it to let you know that I have had multiple failures with drivers in this application.

The oscilloscope pictures have been made into a powerpoint (21mb), you can download them from https://drive.google.com/open?id=1nlpuCNPgn9C2LMH-RJehQwbQ5_Q2hv2O

The IRS2007 is a bit hard to reach on my board because the mosfets are mounted on heatsinks. For now the waveforms are taken from the most accessable points on the circuit, the mosfet Gate for the gate pulses and the connection point from the microcontroller board to the respective phase board for the input signals.
Please go through these waveforms and then based on your inputs, I will capture the waveforms from different points of the mosfet driver.
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Emanuel
Employee
10 solutions authored 5 solutions authored First solution authored
Employee
Hi Sujoy,

Thank you for the effort of making the powepoint.
I will have to ask you to please attach the images here. Unfortunately, due to security reasons we cannot access file sharing services.
Regards,
Emanuel
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sujoy
Level 2
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Level 2
can you download it from https://www.electrineingenum.com/blank-page

Its just a bunch of oscilloscope images with some explaination.

I tried uploading it here but 21MB was a bit too much.
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sujoy
Level 2
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Hi Emanuel, can you please let me know if you could access the document or not.
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Emanuel
Employee
10 solutions authored 5 solutions authored First solution authored
Employee
Hi Sujoy. Please see PM.
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Emanuel
Employee
10 solutions authored 5 solutions authored First solution authored
Employee
Hi Sujoy,

could you please confirm that it's always the phase U that is failing. in this case it might be related to how the layout is done and how the signals are routed.
you are also using a 0R turn off. is there any reason why you have such a fast ramp? This might cause noise in the circuit if proper shielding is not present.
You posted also a video and some signal, please change triggering from Auto to normal so we can see the edges.
It also seems that for a 12V system you have quite a high noise on the signals. with gate peaks reaching 80 V.
Looking at the U phase HIN propagating to the LO output, for me, it looks like when you disconnect your LIN pin, due to noise it gets pulled low (the internal pull-up seem to not be sufficient). As the gate driver has a deadtime and shoot-through protection (page 7), this might get activated. If LIN gets LOW and HIN goes HIGH both outputs get turned off. You can replicate this by measuring both both outputs or you can connect LIN to VCC and see if this still happens.

Also please perform the measurements I have asked you above:


Please measure:

HIN-COM
LIN-COM
LO-COM
HO-COM

Then also measure:
VIN-COM
HIN-COM
VB-COM
HO-COM

with and without V_POW (please also mention V_POW used). The measurements should be done on the gate driver pins.

it seems you only have a 2 channel scope available. Please use normal triggering with normal coupling.

so I would split it like this:

LIN-HIN (trigger on LIN 50% rising)
LIN-LO (trigger on LIN 50% rising)
HIN-HO (trigger on HO 50% falling)

please do this with both V_POW and without V_POW connected, but without any load for the moment.
just to understand the behavior.
P.S. 1-2 Switching periods are better as we can see the deadtime and how the signals interact.
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sujoy
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Hi Emanuel, please find the answers below:-

1. U Phase failure - I have not changed the problematic IC yet. I wanted to show you the issue. With the previous version of the circuit, (with bjt) on turn on any 1 phase would fail randomly. The drivers for all 3 phases failed twice each before I removed the BJTs and used only the mos Driver. When the mos driver also failed, I thought there is some other issue. BTW before this error, the U phase and W phase had driven the motor in a 2 phase config. Even this time, the system worked for about 1 min before the U phase died.

2. 0R turn off - Mainly because I wanted the current to be only limited by the IRS2007 internal mosfets. Since I had failures at 54mA (12V 220Ohm) I presumed that the rated current for rise and fall was of an instantaneous nature and prolonging the current through the device was causing it to fail. Also your datasheet shows IRS2007 pins connected directly to Mosfet Gates.

3. Fast turn on - In one previous design, I used a opto-coupler to pass on signals to the high side gate and the rise time was 4us and fall time was about 10us. This worked well till 36V and the mosfets exploded at 48V. I presumed it was due to cross conduction so I worked to reduce the switch on/off time. Also longer switching times mean more switching losses so I was trying to avoid that. If required, I'll change that.

4. Shielding - I tried to ensure that all signals have ground traces on each side to ensure some kind of shielding. Also bypass capacitors are present at the input side. The bypass capacitors at the gate side were removed to reduce current load on the IRS2007s

5. Video triggering - Will do. The video was for V_in vs V_boost

6. Gate peaks reach 80V - I presumed it was an error or something. If you want, I can focus more on why that is happening. Note that this happens when the motor is running.

7. U Phase HIN propagating to LO output - It is actually LIN propagating to HO output. Also I'm not sure what you mean by "noise" at that point motor is stalled and waveform seems clean. I think, I had tested the LIN pin voltage as well and it was high. If you want, I can check again and confirm.

8. Gate driver deadtime protection - I know I have both read and verified this.

9. Oscilloscope measurements- I have a 2 channel scope with basic probes not differential ones. I'll get these in a couple of hours.

10. No load connected - Do you mean the motor should be disconnected? Then HO will always show 12V (V_in) if LO is off because of the bootstrap action. I can still try or maybe add a 10k resistor as load.

11. P.S 1-2 switching behaviour - I did not understand this.

12. Switching scheme from microcontroller - (Position is from sensor withing the motor) '+' means high side on, '-' means low side on
Position 1 - U+ V-
Position 2 - U+ W-
Position 3 - V+ W-
Position 4 - V+ U-
Position 5 - W+ U-
Position 6 - W+ V-
Then on to Position 1

13. The noise is when the motor was running with V phase and W phase on.
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Emanuel
Employee
10 solutions authored 5 solutions authored First solution authored
Employee
HI Sujoy,

this is becoming a bit confusing. you provided a lot of images but not too much towards what I am looking for 🙂
0. Right now I am trying to localize the problem, this is why I am trying to simplify the circuit and remove the impact. I want to see what the problem with the gate driver is. Thus it would be helpful if the uC is just generating the PWM for this phase so we can see if there is some problem there.
1. still did not managed to understand if only U phase is problematic or all.
2. 0R is usually a aggressive. even in the datasheet we do have some resistors drawn in the typical application. What is the switching frequency? we might need to look into the thermal loading of the gate driver.
3 & 4 & 6. this were guessing as I did not see the circuit. But the spikes in some of the images tend to make me look into that direction.
5. -
7. on slide 21 you showed the HI input and the output. For this to happen it can be 3 reasons:
- Gate driver is damaged. I believe you checked this by performing the measurements on a good/new GD
- Bootstrap capacitor is getting discharged. -from the waveform it doesn't look like it. Also, it would not restart
- Shoot-through protection gets triggered. -> this would mean that the LIN goes LOW. but from the looks of it, it seems to be really periodical. so here you would need to be able to see also how the rest of the pins are behaving or to force the LIN high from the uC.
8. ok. would still be nice to see the micro-controller sequence see 0.
9. ok. while AC coupling is great for higher voltages. for the voltage levels you are working at, DC coupling would show more information, please use DC coupling with normal trigger.
10. Yes. please remove the motor. adding a 10kohm resistor would not be a problem, i just want to see the switching without a motor connected, with both DC-link (V_POW) connected and disconnected.
the bootstrap cap is charged when the lower MOSFET (LO) is turned on. once LO turns off, and HO gets turned on, the boostrap capacitor gets discharged by the higher gate capacitance.for as long as the bootstrap cap is calculated correctly (and it seems it is) and the lower mosfet is switched, we should not have a problem with charge of the capacitor.
11. You show a lot of switching periods in your picture. This is good. put please also do the same measurements while showing only 1 or 2 (max) switching periods (have a lower t/division). this would allow us to better see the deadtime between pulses, and propagation delays.
12 & 13, noted, please see 0. above. most interest for me is to see the switching of a gate driver (HO/LO) and interaction in the half-bridge.
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sujoy
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Hi Emanuel,

Sorry I am just throwing all information I can at you in the hope that something sticks.

0. Do you want something like 10% off - 40% Low On - 20% off - 30% High on? I can do that. Or tell me how you want the wave.

1. No its random.

2. Switching frequency about 2.5 kHz. Let me know if you want me to remove the reverse diode and only use 10 ohm resistor.

3.,4,6. Original circuit attached here BJTs and spaces for resistors are shorted. Capacitor present at input. Output capacitor open. Board picture is attached in first post.

5. Will do.

7. That is the crazy part. Focus on Slide 22. LIN is the output for HO. HIN is held high and LO is held low. Slides 1-22 in "IRS2007 issue-2.pptx" are for the same damaged gate driver in U phase.
Bootstrap capacitor is not being discharged, I checked (it is about 1000x oversized).

Rest all noted. Once you reply to required waveform, I'll upload relevant pics.


Just to show you that noise is seen only when motor is running.
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Emanuel
Employee
10 solutions authored 5 solutions authored First solution authored
Employee
Hi Sujoy,

no problem.
0. whatever switching duty cycle you use is good for me. this should not be a problem.
2. Fsw or resistance should not be a problem.
3. input cap should not be a problem. output cap will only load the driver, and depending on the inductance in your PCB might resonate.
7. if the blue line is LIN (Active low). and the yellow is HO, i will assume HIN is help high from the image.
If you try to turn on both channels (HO&LO=high) by activating both input (HIN=High, LIN=low) then both channels will get turned off.

the logic matrix is as following:
1=Vcc; 0=GND;

HIN=0;LIN=0 --> HO=0; LO=1;
HIN=1;LIN=1 --> HO=1; LO=0;
HIN=1;LIN=0 --> HO=0; LO=0;
HIN=0;LIN=1 --> HO=0; LO=0;

thus in order for the HO to follow exactly LIN (active LOW) HIN must be held high.
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sujoy
Level 2
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Hi Emanuel,

The problem's solved thanks to your idea. I needed to add a capacitance between V_pow and Ground on each of the 3 phases.

Since I was mostly working on low currents, I hadn't added an input capacitor or considered the length of the wire from the battery to the boards. Supposedly due to the wire inductance, when the high side mosfet turned off, there was a short, sharp voltage spike on the V_pow line.

That is why the motor would run with 2 phases as there were only 2 current carrying switching actions per cycle. When 3 phases were activated, I speculate that one mosfet would turn on during the V_pow peak and maybe damage the gate driver due to dV/dt or something.

It was your idea of switching the mosfet without load with V_pow connected that lead me to the answer. Thanks man.

Until my next issue, take care.
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Emanuel
Employee
10 solutions authored 5 solutions authored First solution authored
Employee
Hi Sujoy,

glad we could help, even indirectly :). Somehow we overlooked the missing decoupling caps. But yes, ideally they should be as close as possible to the switches and the switching path kept as low inductive as possible.
You should also look into decoupling VCC and the bootstrap cap. The later is quite far away from the pins so the added inductance is not that good.
Do you know how large the spikes were?
I do not think that the the spikes would of coupled and damaged the driver (they should of been really high).
Did you by any chance also measured the middle point (VS) in reference to COM? did it went negative? how negative?
Most likely the Vs point went negative (in reference to COM) due to the very high inductance in the supply/switching path and this damaged the driver IC. This is an inherent problem of level-shift gate drivers, especially the "Junction Isolated" (Bulk CMOS) gate drivers, and while our technology is one of the most robust on the market, for this product we can generally allow COM - 8 V on the VS pin.
I think decoupling the 3 phases actually solved this negative spikes.
Please let me know if this problem reapers 🙂
Good luck with your project.
Best regards,
Emanuel
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